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Active Keyword: Power Verification Remove filter Clear all

13 of up to 20 (filtered)

Low-Power & CDC Verification Engineer

Amd

Santa Clara, CA 12 days ago $118,400–$177,600
Actively hiring Confirmed live today High trust Below market
Formal Verification RTL Power/Clock Domain Crossing UPF Python Perl Simulation Emulation Digital Design Processor Architecture Tape out Verification
1+ yrs exp
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Power Management Systems Design and Verification Engineer

Qualcomm

San Diego, CA 32 days ago $99,500–$149,300
Actively hiring Confirmed live today High trust Below market
PMIC Systems Power Electronics Python MATLAB Mentor Graphics PCB Layout Firmware SMPS LDO Buck Converters Boost Converters Post-silicon Verification Thermal Analysis Power Distribution Networks PWB Design Excel
1+ yrs exp
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Senior Design Verification Engineer, Power DVT Team

Amazon Inc

Redmond, WA 39 days ago $137,300–$185,700
Actively hiring Confirmed live today High trust Below market
Power Electronics Hardware Validation DFT SI/PI FPGA Firmware Test Automation I2C SPI CAN DO-160 MIL-STD-810 Requirements Management Radiation Testing
5+ yrs exp
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CPU Debug and Power Management Verification Engineer

Apple Inc

Beaverton, OR 40 days ago
Actively hiring Confirmed live today Low trust
SystemVerilog UVM SVA Python Perl C++ Assembly AXI UPF FPGA Emulation Formal Verification Post-Silicon Debug Power Management Clock Control RTL Simulation
3+ yrs exp
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CPU Debug and Power Management Verification Engineer

Apple Inc

Beaverton, OR 40 days ago
Actively hiring Confirmed live today Low trust
SystemVerilog UVM SVA Python C++ Assembly Perl AXI FPGA Emulation Formal Verification UPF Low Power Simulation Post-Silicon Debug
10+ yrs exp
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CPU Processor Power Management Verification Engineer

Apple Inc

Santa Clara, CA 40 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Trusted Above market
System Verilog Verilog UVM Python Perl Assembly Formal Verification UPF FPGA Emulation RTL Digital Logic Power Management Clock Control
10+ yrs exp
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CPU Processor Power Management Verification Engineer

Apple Inc

Santa Clara, CA 40 days ago $150,400–$277,600
Actively hiring Confirmed live today Trusted Competitive pay
System Verilog Verilog UVM Python Perl Assembly Formal Verification UPF FPGA Emulation RTL Digital Logic Power Management Clock Control Simulation Testbenches Transactors Assertions
3+ yrs exp
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CPU Processor Power Management Verification Engineer

Apple Inc

Santa Clara, CA 40 days ago $129,300–$194,700
Actively hiring Confirmed live today Trusted Below market
System Verilog Verilog Python Perl TCL Assembly Formal Verification FPGA Emulation RTL Computer Architecture Digital Logic Power Management Clock Control Testbenches Transactors Assertions
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CPU Processor Power Management Verification Engineer

Apple Inc

Santa Clara, CA 40 days ago $150,400–$277,600
Actively hiring Confirmed live today Trusted Competitive pay
System Verilog Verilog UVM Python Perl Assembly Formal Verification UPF FPGA Emulation RTL Digital Logic Power Management Clock Control Random Constraint Verification
3+ yrs exp
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CPU Processor Power Management Verification Engineer

Apple Inc

Santa Clara, CA 40 days ago $129,300–$194,700
Actively hiring Confirmed live today Trusted Below market
System Verilog Verilog Python Perl TCL Assembly Formal Verification FPGA Emulation RTL Computer Architecture Digital Logic Power Management Clock Control Testbenches Transactors Assertions
Save

CPU Processor Power Management Verification Engineer

Apple Inc

Santa Clara, CA 40 days ago $184,700–$324,800
Actively hiring Confirmed live today Trusted Above market
System Verilog Verilog UVM Python Perl Assembly Formal Verification UPF FPGA Emulation RTL Digital Logic Power Management Clock Control
10+ yrs exp
Save

CPU Debug and Power Management Verification Engineer

Apple Inc

Beaverton, OR 40 days ago
Actively hiring Confirmed live today Low trust
SystemVerilog UVM SVA Python Perl C++ Assembly AXI UPF FPGA Emulation Formal Verification Post-Silicon Debug Simulation Power Management Clock Control Hardware Trace
10+ yrs exp
Save

CPU Debug and Power Management Verification Engineer

Apple Inc

Beaverton, OR 40 days ago
Actively hiring Confirmed live today Low trust
SystemVerilog UVM SVA Python C++ Assembly Perl AXI UPF FPGA Emulation Formal Verification Post-Silicon Debug Power Management Clock Control RTL Simulation
3+ yrs exp
Save