Low-Power & CDC Verification Engineer

Amd

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $118,400–$177,600 / yr
Posted: 12 days ago
Freshness: Confirmed live today
Closes: Oct 15, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $195k

This role $148k

$106k $238k

below market most similar roles pay here above market

This role pays less than 91% of similar roles. Most pay $167,791–$222,500 — the blue band above. At the midpoint, this role pays about $148k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

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At a glance

TL;DR · Low-Power & CDC Verification Engineer

Role Posting Log in to save

As a Low-Power & CDC Verification Engineer, you will join the team to work alongside formal experts and designers to verify formal properties and drive convergence. Your daily responsibilities include reviewing power features for verification scoping, writing test plans, and coordinating with various teams to develop verification components using different methodologies. You will review and sign off on verification deliverables for project milestones while working with the RTL team to debug and sign off on power and clock domain crossing violations. The role requires experience in simulation, emulation, and formal verification environments, specifically involving UPF and power/clock domain crossing. You should possess scripting skills in Perl or Python and a background in computer or electrical engineering to solve complex processor architecture and digital design problems.

Skills

Formal Verification RTL Power/Clock Domain Crossing UPF Python Perl Simulation Emulation Digital Design Processor Architecture Tape out Verification

What you'll do

Review power features to define verification scoping and write test plans.
Coordinate with various teams to develop verification components using different methodologies.
Review and sign off on verification deliverables for power features at project milestones.
Debug and sign off on power and clock domain crossing violations with the RTL team.
Verify formal properties in collaboration with formal experts and designers.
Drive convergence of verification goals across the design lifecycle.

What we're looking for

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.
Strong analytical and problem-solving skills.
Excellent communication skills and a team-oriented mindset.
At least 1 year of experience in feature verification from high-level design to tape-out (preferred).
Experience working in simulation, emulation, and formal verification environments (preferred).
Exposure to Power/Clock domain crossing and UPF (preferred).
Scripting skills in Perl or Python (preferred).
Leadership skills (preferred).

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