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MATLAB Simulink Model-Based Systems Engineering IBM Rational DOORS C C++ Assembly Java VHDL Verilog SystemVerilog SystemC RS-232 I2C SPI PCIe Ethernet SRIO Xilinx Microsemi Texas Instruments Intel Visual Studio Qt Jira Git Agile EVMS Microsoft Project +24 more Show less

ASIC RTL Verilog VHDL System Verilog UPF CPF Conformal Low Power Check Python Tcl Perl DFT Synthesis Timing Closure Power Analysis Power Modeling Prime Power PowerArtist PtPx +14 more Show less

PMIC Power Management Systems VerilogAMS VerilogA VerilogPLI EDA Tools SPICE MATLAB Verilog VHDL C Python C# F# PCB Design DC-DC Converters Mixed-Signal JTAG +13 more Show less

PCB Design OrCAD Allegro PowerSI SiWave Simplis PSpice HSpice Control Theory Circuit Modeling High Frequency Magnetics Buck/Buck-Boost Regulators PWM Controllers LDOs PMICs Oscilloscope SVIx +12 more Show less

Power Management ICs Cadence ADE Spectre MATLAB Verilog Verilog‑AMS SystemVerilog VHDL SPICE Simplis Control Theory Power Electronics Silicon Characterization +8 more Show less

VLSI RTL Design micro architecture Synthesis Silicon Engineering Power Control Systems ASIC +2 more Show less

Power Management ICs Cadence ADE Spectre MATLAB Verilog Verilog‑AMS SystemVerilog VHDL SPICE Simplis Control Theory Power Electronics Behavioral Modeling Silicon Characterization +9 more Show less

Power Modeling Circuit Simulation Analog and Digital Circuits Power Delivery Networks (PDN) Ansys Sigrity Matlab Simulink Simplis Spice verilogAMS Cadence Virtuoso Allegro HSpice Spectre Primesim Python Tcl Perl Skill +15 more Show less

Matlab Simulink Python C++ ANSYS Saber Sherlock CFD FEA PSpice MathCAD MIL SIL HIL VIL CAE DFMEA DRBFM Agile SAFe +15 more Show less

Power Modeling Python Matlab Multimeters Oscilloscopes Logic Analyzers Analog Circuits Power Electronics Data Analysis Control Systems Scripting +6 more Show less

Physical Design TCL Python ASIC Integration Floorplanning Power Distribution Signal Planning I/O Planning Hard IP Integration Tapeout Voltage Drop Analysis STA Layout Verification DRC CAD +10 more Show less

Physical Design TCL Python ASIC Integration Floorplanning Power Distribution Signal Planning I/O Planning Hard IP Integration Tapeout Voltage Drop Analysis STA Layout Verification DRC CAD Scripting +11 more Show less

Physical Design TCL Python ASIC Integration Floorplanning Power Distribution Tapeout Voltage Drop Analysis Layout Verification DRC CAD Scripting +7 more Show less

ASIC Design Low Power Design RTL ARM IP AMBA AHB APB AXI PCIe USB 802.11x Synthesis Timing Closure Emulation Power Intent post silicon bring up +11 more Show less

ASIC RTL Verilog System Verilog UPF CLP STA Python Tcl Perl Make ISO 26262 FMEA FMEDA Simulation Emulation SoC Architecture +12 more Show less

Mixed-Signal IC Design CMOS FinFET Cadence SPICE MATLAB Verilog VHDL ASIC Layout Data Converters PLL Analog Design Automation ATE Verification +10 more Show less