ASIC Design Engineer
Qualcomm
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How this pay compares to similar roles
This role pays more than 76% of similar roles. Most pay $153,043–$216,562 — the shaded band above. At the midpoint, this role pays about $220k versus about $185k for comparable roles.
Based on 240 similar postings.
Employer
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 623 open roles on FindRole.
Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.
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At a glance
As a Design Engineer (Low Power) within the Integrated Wireless Technology team, you will focus on WiFi technology, SOC Design, and low power micro-architecture. You will be responsible for developing technical specifications from architectural requirements to deliver detailed designs while collaborating with verification teams on plans and debug phases. Your daily work involves owning designs through the full ASIC development process, including RTL implementation, synthesis, timing closure, emulation, and post-silicon bring up. Key responsibilities include silicon power measurements, power correlation, and full chip debug using ARM IPs. You will utilize skills in Power Intent, power estimation tools, and reduction techniques. The role requires expertise in multi-domain clocking, AMBA bus protocols like AHB and APB, and AXI. Experience with PCIe, USB peripherals, and CPU subsystem-based design is also relevant to this technical domain.
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