Design Engineer (Low Power)

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$190,200–$285,400 / yr
Posted
40 days ago
Freshness
Confirmed live yesterday
Closes
Mar 16, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $194k
This role $238k
$127k $302k
below market most similar roles pay here above market

This role pays more than 77% of similar roles. Most pay $159,700–$229,100 — the blue band above. At the midpoint, this role pays about $238k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

Most-posted roles

View all roles at Qualcomm

At a glance

TL;DR · Design Engineer (Low Power)

Role Posting Log in to save

Design Engineer (Low Power) joins the Integrated Wireless Technology team to work on WiFi 802.11x technology and SOC Design. The role involves developing technical specifications from architectural requirements to deliver detailed low power micro-architecture and design. Key responsibilities include owning the design through the full ASIC development process, including RTL implementation, verification, synthesis, timing closure, emulation, and post silicon bring up. The candidate will perform silicon power measurements, power correlation, and full chip debug using ARM IPs. Required expertise includes SoC low power micro-architecture, power intent, power estimation, multi-domain clocking, and AMBA bus protocols like AHB and APB. Preferred skills include AXI, PCIE, USB peripherals, and CPU subsystem-based design. This position addresses critical power reduction techniques and micro-architecture challenges within wireless technology products.

Skills

ASIC Design Low Power Design RTL Synthesis Timing Closure ARM IP AMBA AHB APB AXI PCIe USB silicon bring up Power Analysis Emulation SoC micro architecture 802.11x Multi-domain Clocking

What you'll do

  • Develop technical specifications from architectural and systems requirements.
  • Deliver detailed low power micro-architecture and design for WiFi technology.
  • Own the design through the full ASIC development process from specification to post-silicon bring-up.
  • Perform RTL implementation, synthesis, timing closure, and emulation.
  • Develop verification plans and participate actively in the debug phase.
  • Conduct silicon power measurements, Si debug, and power correlation.
  • Execute full chip debug design using ARM IPs.

What we're looking for

  • Bachelor's degree with 6+ years of experience, Master's with 5+ years, or PhD with 4+ years in ASIC design, verification, validation, or integration.
  • 7+ years of working experience in ASIC Design.
  • 2+ years of experience in low power micro-architecture, design, power intent/implementation, power optimization, and power estimation.
  • Experience in silicon bring up and debug is a must.
  • Required experience in SoC micro architecture, multi-domain clocking, and AMBA bus protocols such as AHB and APB.
  • Experience in ARM IP based full chip debug is preferred.
  • Experience in PCIE/USB peripherals is preferred.
  • Experience in CPU sub system-based design is preferred.

Related searches

More Design Engineer jobs Design Engineer jobs in Santa Clara All jobs at Qualcomm

More like this

Similar roles

Systems Power Design Engineer

Amd

Austin, TX 97 days ago $133,200–$199,800
System Power Modeling C/C++ Python Perl Ruby System Architecture Power Management Logic Analyzers Oscilloscopes Scripting Hardware Modeling Validation Strategies SOC APU
Save

Design Engineer

Ramp

New York City, NY 111 days ago $172,000–$440,000
React TypeScript JavaScript HTML CSS Figma Cursor Claude LLM Design Systems Core Web Vitals Accessibility Headless CMS Design Tokens
Hybrid
Save

Design Engineer

Broadcom

Fort Collins, CO 54 days ago
ASIC Design VLSI CMOS Physical Design Floorplanning Placement Clock Tree Synthesis Routing Timing Closure DRC LVS IR/EM Checks RTL to GDSII UNIX Linux TCL Python Perl Cadence Innovus Synopsys ICC2 PrimeTime
Save

Design Engineer

Broadcom

Fort Collins, CO 7 days ago $61,900–$99,000
ASIC Design IC Design Floor Planning Routing Timing Analysis Physical Verification SerDes Signal Integrity Power Integrity CMOS Clocking Structures
Save

Design Engineer

Broadcom

Fort Collins, CO 7 days ago $61,900–$99,000
ASIC Design IC Design Floor Planning Routing Timing Analysis Physical Verification Signal Integrity Power Integrity SerDes CMOS Clocking Structures
Save