Design Engineer (Low Power)

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$176,300–$264,500 / yr
Posted
72 days ago
Freshness
Confirmed live yesterday
Closes
Dec 28, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $185k
This role $220k
$129k most similar roles pay here $279k

This role pays more than 76% of similar roles. Most pay $153,043–$216,562 — the shaded band above. At the midpoint, this role pays about $220k versus about $185k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Design Engineer (Low Power)

As a Design Engineer (Low Power) within the Integrated Wireless Technology team, you will focus on WiFi technology, SOC Design, and low power micro-architecture. You will be responsible for developing technical specifications from architectural requirements to deliver detailed designs while collaborating with verification teams on plans and debug phases. Your daily work involves owning designs through the full ASIC development process, including RTL implementation, synthesis, timing closure, emulation, and post-silicon bring up. Key responsibilities include silicon power measurements, power correlation, and full chip debug using ARM IPs. You will utilize skills in Power Intent, power estimation tools, and reduction techniques. The role requires expertise in multi-domain clocking, AMBA bus protocols like AHB and APB, and AXI. Experience with PCIe, USB peripherals, and CPU subsystem-based design is also relevant to this technical domain.

What you'll do

  • Develop technical specifications from architectural and system requirements for low power micro-architecture.
  • Implement low power design techniques including Power Intent, estimation, and reduction strategies.
  • Own the full ASIC development process from specification and RTL implementation to synthesis and timing closure.
  • Collaborate with verification teams to develop plans and participate in the debug phase.
  • Perform silicon power measurements, silicon debugging, and power correlation.
  • Execute full chip debug designs using ARM IPs.
  • Manage design integration for multi-domain clocking and AMBA bus protocols like AHB, APB, and AXI.

What we're looking for

  • Bachelor's degree with 6+ years of experience, Master's with 5+ years, or PhD with 4+ years in ASIC design and related fields.
  • At least 7 years of working experience in ASIC Design.
  • At least 2 years of experience in low power micro-architecture, design, Power Intent/Implementation, and power estimation.
  • Experience in silicon bring up and debug is a must.
  • Required experience in SoC micro architecture, multi-domain clocking, and AMBA bus protocols such as AHB and APB.
  • Experience in ARM IP based full chip debug (preferred).
  • Experience in PCIE/USB peripherals or CPU sub system-based design (preferred).
  • Experience in low power design from project start to volume chip production for at least one product cycle (preferred).

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