RTL Design Engineer, Power Design

Amd

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Austin, TX
Salary: $200,000–$300,000 / yr
Posted: 9 days ago
Freshness: Confirmed live yesterday
Closes: Sep 22, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $190k

This role $250k

$127k most similar roles pay here $319k

This role pays more than 88% of similar roles. Most pay $162,559–$217,912 — the shaded band above. At the midpoint, this role pays about $250k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 374 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 374 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · RTL Design Engineer, Power Design

Role Posting Log in to save

The RTL Design Engineer – Power Design joins the Security IP design team to develop and verify embedded microprocessor subsystems and hardware accelerators for System-on-Chip products. In this role, you will define IP-level power specifications, track power targets, and drive optimization efforts in collaboration with SoC and measurement teams. You will also work with corporate methodology teams to enhance advanced power design flows and infrastructure. Key responsibilities include developing power vectors for simulation, monitoring health metrics, and providing technical leadership in power architecture. The role requires proficiency in Verilog, SystemVerilog, and scripting languages like Python, Tcl, Perl, or Ruby within Makefile environments. Candidates should possess deep knowledge of RTL-level power design, microprocessor microarchitectures, and industry-standard protocols such as AMBA, AXI, and AHB to solve complex power challenges across diverse hardware applications.

Skills

Verilog SystemVerilog Python Tcl Perl Ruby Makefile AMBA AXI AHB ASIC Design RTL Simulation Linting Synthesis Power-aware Verification Low-power Design SoC Microarchitecture

What you'll do

Develop and maintain RTL-level IP power specifications aligned with SoC requirements.
Define, track, and drive IP power targets by correlating design intent with measurement results.
Collaborate with verification teams to develop power vectors for simulation-based measurements.
Partner with static power measurement teams to develop regression infrastructure and debug power issues.
Implement advanced power architecture, design, and analysis methodologies in collaboration with corporate teams.
Influence SoC power strategy and contribute to the development of corporate power methodologies.
Provide technical leadership and mentorship regarding power architecture and best practices.

What we're looking for

Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Proficiency in Verilog/SystemVerilog and scripting languages such as Python, Tcl, Perl, and Ruby (preferred).
Deep knowledge of modern RTL-level power architecture, design, analysis, measurement methodologies, and industry best practices (preferred).
Strong understanding of microprocessor subsystem architectures, datapath accelerator microarchitectures, and low-power design methodologies (preferred).
Solid understanding of industry-standard on-chip bus and interface protocols like AMBA, AXI, and AHB (preferred).
Experience with ASIC design and verification tools including RTL simulation, linting, synthesis, and power-aware verification (preferred).
Demonstrated ability to collaborate across IP, SoC, methodology, and verification teams to drive technical solutions (preferred).

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