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System Verilog UVM VCS C C++ Python Perl Shell ASIC Verification RTL FPGA Debussy GDB DDR LPDDR +10 more Show less

RAS PCIe CXL Memory MCA JTAG Python C++ Perl Ruby post silicon validation Protocol Analyzers Debug Scripts SOC Micro-Controller +10 more Show less

ASIC Design RTL Coding Digital Design HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Gate Level Simulation Synthesis Timing Closure Power Analysis Hardware Architecture +11 more Show less

C C++ CUDA Parallel Computing Linux Windows Kernel Mode Development Virtual Memory System Software PyTorch Multi-node Scalability Operating System Interfaces +7 more Show less

CUDA C C++ Linux Kernel Mode Drivers Memory Management Windows macOS Driver Development Virtual Memory Process Control +6 more Show less

Python Go Scala Java C++ C# AWS Huggingface PyTorch VectorDBs Nemo Guardrails LLM Inference Similarity Search Machine Learning Gen AI SaaS Observability +12 more Show less

3D Memory ASIC Design RTL Verilog Verilog-A Verilog-AMS C C++ Python Perl Matlab EDA Tools HBM3/4 LPDDR PCIe UCIe UAL SRAM DRAM FLASH 2.5D/3D Integration +16 more Show less

System Architecture x86 NVMe PCIe CXL Infiniband Ethernet DDR Cloud-Native Computing SoC Design BIOS AI Training Inference UCIe SmartNICs RAID +11 more Show less

Verilog System Verilog HLS RTL Microarchitecture Computer Architecture Memory Controller NoC Interconnect IP SoC Integration AI/ML Pipelining Data Compression +8 more Show less

UVM System Verilog Python Formal Verification PCIe CXL AMBA CHI JEDEC Memory Controller Generative AI Verification Methodology +7 more Show less

SystemVerilog UVM Verilog SystemVerilog Assertions ASIC SoC Formal Verification UPF AXI APB AHB DFI JEDEC DDR LPDDR HBM Constrained-Random Verification Coverage-Driven Verification Simulation Waveform Analysis +15 more Show less

Semiconductor Manufacturing CMOS Logic FEOL MEOL BEOL Logic Memory NAND DRAM Process Engineering Hardware Characterization Technical Documentation +7 more Show less

HBM DDR5 LPDDR NVMe Semiconductors Datacenter Infrastructure Procurement Sourcing Demand Forecasting Capacity Planning Should-cost Analysis Financial Modeling +7 more Show less

ASIC Design RTL Coding HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Digital Design Hardware Architecture +11 more Show less

ASIC Design RTL Coding HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Digital Design Hardware Architecture +11 more Show less

ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Validation Scripting SoC +5 more Show less

Verilog SystemVerilog ASIC Design RTL Synopsys Synthesis Low Power Design Computer Architecture C C++ Python Design Verification SOC Interconnects Memory Subsystems +8 more Show less

System Verilog UVM VCS C++ C Python Perl Shell FPGA RTL Post-silicon Verification DDR LPDDR HBM GDDR GDB Debussy +12 more Show less

DRAM NAND Procurement Market Intelligence Contract Negotiation Forecasting Excel Power BI Tableau Process Improvement Supplier Relationship Management Analytics +7 more Show less

HBM DDR5 LPDDR NVMe Semiconductors Procurement Sourcing Demand Forecasting Capacity Planning Should-cost Analysis Financial Modeling Datacenter Infrastructure AI Infrastructure +8 more Show less