Distinguished Technologist, Memory/Storage Utilization & Data Placement Architect

HP Inc.

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Spring, TXPalo Alto, CA
Salary
$190,000–$274,000 / yr
Posted
93 days ago
Freshness
Confirmed live yesterday
Closes
Dec 7, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $222k
This role $232k
$156k most similar roles pay here $301k

This role pays more than 53% of similar roles. Most pay $188,187–$254,943 — the shaded band above. At the midpoint, this role pays about $232k versus about $222k for comparable roles.

Based on 240 similar postings.

Employer

About HP Inc.

HP Inc. is a global technology company that develops and sells personal computers, printers, and related supplies and services. Its products include laptops, desktops, workstations, and printing solutions for consumers and businesses worldwide.

HP Inc. currently has 104 open roles on FindRole.

Listed pay typically runs $130,700–$205,200 across 90 roles with salary data.

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At a glance

TL;DR · Distinguished Technologist, Memory/Storage Utilization & Data Placement Architect

Distinguished Technologist - Memory/Storage Utilization & Data Placement Architect serves as a technical authority defining how memory and storage are jointly utilized as a unified data hierarchy for AI workloads. The role involves architecting memory and storage hierarchies including DRAM, SSD, and cache layers while defining policies for data placement and movement across hot and cold tiers. Key responsibilities include optimizing paging, prefetching, and streaming for AI inference and training, alongside enabling efficient use of storage as memory extension through KV cache strategies. This position requires expertise in computer engineering, hardware architecture, and electrical design to develop technology roadmaps and solve complex problems regarding data orchestration. The role utilizes skills in MATLAB, FPGA, and systems design to address the technical challenge of co-optimizing models across memory and storage for maximum performance in high-demand AI environments.

What you'll do

  • Architect a unified memory and storage hierarchy including DRAM, SSD, and cache layers for AI workloads.
  • Define policies for data placement and movement across different storage tiers.
  • Optimize paging, prefetching, and streaming specifically for AI inference and training performance.
  • Enable the use of storage as a memory extension through spillover and KV cache strategies.
  • Partner with software teams to co-optimize models across memory and storage layers.
  • Evaluate emerging technologies such as unified memory, memory pooling, and data compression.
  • Develop long-term technology roadmaps and strategic visions for electrical hardware design.
  • Lead industry-leading research and development initiatives to identify future growth opportunities.

What we're looking for

  • A four-year or graduate degree in Electrical Engineering or a related discipline is required.
  • Candidates should have 12+ years of experience in electrical design, hardware architecture, or a related field.
  • Expertise in memory and storage hierarchy architecture including DRAM, SSD, and cache layers is required.
  • Proficiency in computer engineering, computer science, and electronic engineering is required.
  • Experience with hardware design, systems design, and new product development is required.
  • Skills in debugging, simulations, and schematic capture are required.
  • Knowledge of FPGA technology and MATLAB is preferred.
  • Strong communication skills and the ability to provide technical leadership and mentoring are required.

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