Distinguished Technologist, Memory/Storage Utilization & Data Placement Architect

HP Inc.

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Quick summary

Work type
On-site
Location
Spring, TXPalo Alto, CA
Salary
$190,000–$274,000 / yr
Posted
13 days ago
Freshness
Confirmed live today
Closes
Apr 12, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $221k
This role $232k
$154k $291k
below market most similar roles pay here above market

This role pays more than 54% of similar roles. Most pay $188,525–$253,500 — the blue band above. At the midpoint, this role pays about $232k versus about $221k for comparable roles.

Based on 240 similar postings.

Employer

About HP Inc.

HP Inc. is a global technology company that develops and sells personal computers, printers, and related supplies and services. Its products include laptops, desktops, workstations, and printing solutions for consumers and businesses worldwide.

HP Inc. currently has 115 open roles on FindRole.

Listed pay typically runs $130,700–$205,200 across 95 roles with salary data.

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At a glance

TL;DR · Distinguished Technologist, Memory/Storage Utilization & Data Placement Architect

The Distinguished Technologist - Memory/Storage Utilization & Data Placement Architect joins the engineering team to define how memory and storage function as a unified data hierarchy for AI workloads. This role involves architecting DRAM, SSD, and cache layers while defining policies for data placement and movement across hot and cold tiers. Key responsibilities include optimizing paging, prefetching, and streaming for AI inference and training, and enabling storage as a memory extension for KV cache strategies. The position requires expertise in memory design, computer engineering, hardware architecture, and electrical engineering. Candidates must utilize tools and skills including MATLAB, FPGA, schematic capture, and simulations. The work focuses on solving complex data orchestration problems, developing long-term technology roadmaps, and integrating advanced theories to improve performance across multiple hardware disciplines.

What you'll do

  • Architect the memory and storage hierarchy including DRAM, SSD, and cache layers.
  • Define policies for data placement and movement across hot and cold data tiers.
  • Optimize paging, prefetching, and streaming for AI inference and training workloads.
  • Co-optimize AI models with software teams across memory and storage for maximum performance.
  • Enable efficient storage use as memory extension for spillover and KV cache strategies.
  • Collaborate with OS and runtime teams on data orchestration.
  • Evaluate emerging technologies such as unified memory, memory pooling, and compression.
  • Develop technology roadmaps and long-term strategies for electrical hardware design.

What we're looking for

  • A four-year or graduate degree in Electrical Engineering or a related discipline is required, or commensurate work experience.
  • Typically has 12+ years of work experience, preferably in electrical design, tools, software packages, or hardware architecture.
  • Expertise in memory design, computer engineering, computer science, and electrical or electronic engineering is required.
  • Proficiency in hardware architecture, hardware design, systems design, and new product development is required.
  • Skills in MATLAB, simulations, schematic capture, and using an oscilloscope are required.
  • Knowledge of FPGA, physics, and printed circuit boards is required.
  • Strong communication, results orientation, learning agility, digital fluency, and customer centricity are required.
  • Experience in debugging and optimizing data placement for AI workloads is required.

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