Memory Controller Performance Architect

Arm Holdings

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Austin, TX
Salary
$161,500–$218,500 / yr
Posted
19 days ago
Freshness
Confirmed live today

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $222k
This role $190k
$147k $297k
below market most similar roles pay here above market

This role pays less than 71% of similar roles. Most pay $187,850–$255,487 — the blue band above. At the midpoint, this role pays about $190k versus about $222k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 113 open roles on FindRole.

Listed pay typically runs $208,450–$282,050 across 112 roles with salary data.

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At a glance

TL;DR · Memory Controller Performance Architect

The Memory Controller Performance Architect joins a team of performance engineers to drive the development of high-performance interconnect and memory controller IPs for SoC systems. The role involves developing memory controller IP and system models, optimizing power and performance features, and establishing methodologies for new workloads using simulation and emulation. Key responsibilities include conducting system-level analysis to identify bottlenecks, improving IP micro-architecture, and providing guidance to various business units. Candidates must possess a degree in Electrical Engineering, Computer Engineering, or Computer Science with experience in memory/interconnect performance modeling and workload analysis. Required technical skills include C++ programming for large-scale software development and proficiency in Perl or Python scripting. Desired expertise includes SystemC Transaction Level Modeling, interconnect micro-architecture design, and model correlation methodologies with RTL.

What you'll do

  • Develop and analyze memory controller IP and system models to optimize power and performance.
  • Identify system bottlenecks and improve IP micro-architecture through system-level analysis.
  • Create power and performance methodologies for new workloads using simulation and emulation.
  • Provide models, analysis, and design guidance to various business units.
  • Productize performance models for use by external partners.
  • Mentor team members and provide technical leadership on performance modeling.
  • Correlate performance models with RTL designs using SystemC Transaction Level Modeling.
  • Deploy performance tools and develop extrapolation methodologies for large-scale systems.

What we're looking for

  • Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science.
  • Strong experience in computer architecture, microarchitecture, and performance.
  • Proven experience in memory/interconnect performance modeling, workload analysis, and system performance.
  • Proficiency in C++ programming for large-scale software development.
  • Proficiency in Perl or Python scripting languages.
  • Knowledge of SystemC Transaction Level Modeling and interconnect micro-architecture design (preferred).
  • Experience with Model correlation methodologies with RTL (preferred).
  • Experience with performance tools, deployment, and extrapolation methodologies for large systems (preferred).

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