Staff Memory Controller Performance Architect

Arm Holdings

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Quick summary

Work type
On-site
Location
Austin, TX
Salary
$198,100–$268,000 / yr
Posted
21 days ago
Freshness
Confirmed live today

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $219k
This role $233k
$165k most similar roles pay here $287k

This role pays more than 59% of similar roles. Most pay $188,562–$250,000 — the shaded band above. At the midpoint, this role pays about $233k versus about $219k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 106 open roles on FindRole.

Listed pay typically runs $209,100–$282,900 across 106 roles with salary data.

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At a glance

TL;DR · Staff Memory Controller Performance Architect

As a Staff Memory Controller Performance Architect, you will join a team of performance engineers to drive the development of high-performance interconnect and memory controller IPs. You will be responsible for developing and analyzing memory controller IP and system models, optimizing power and performance features based on system-level analysis, and identifying micro-architecture bottlenecks. Your daily work involves creating methodologies for new workloads using simulation and emulation while providing guidance to business units and mentoring team members. The role requires expertise in computer architecture, microarchitecture, and workload analysis. You will utilize C++, Perl, or Python for large-scale software development and scripting. Desired skills include SystemC Transaction Level Modeling, interconnect micro-architecture design, and model correlation with RTL. This role focuses on optimizing AI infrastructure, automotive, and mobile systems by solving complex performance challenges within the Arm ecosystem.

What you'll do

  • Develop and analyze memory controller IP and system models to optimize power and performance features.
  • Identify system-level bottlenecks and improve IP micro-architecture based on key workloads and KPIs.
  • Create power and performance methodologies for new workloads using simulation and emulation techniques.
  • Provide technical guidance, models, and analysis to various business units for optimized system designs.
  • Productize performance models for use by external partners.
  • Mentor team members and provide leadership in performance modeling and analysis.
  • Develop large-scale software and scripts using C++, Perl, or Python for performance analysis.

What we're looking for

  • Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science.
  • Strong experience in computer architecture, microarchitecture, and performance.
  • Proven experience in memory/interconnect performance modeling, workload analysis, and system performance.
  • Proficiency in C++ for large-scale software development.
  • Proficiency in Perl or Python scripting languages.
  • Knowledge of SystemC Transaction Level Modeling and interconnect micro-architecture design (preferred).
  • Experience with Model correlation methodologies with RTL (preferred).
  • Experience with performance tools, deployment, extrapolation methodologies, and mentoring team members (preferred).

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