Browse tech roles

Product Design Interaction Design Visual Design Prototyping design, systems User Flows Wireframes Accessibility Usability Testing React Native JavaScript Component-based UI Design Thinking Analytics AI-assisted workflows +10 more Show less

ASIC Design Physical Design Cadence Innovus Synopsys Fusion Compiler Synopsys PrimeTime SI Python TCL Perl C/C++ Shell Scripting Static Timing Analysis Clock Tree Synthesis DFT Formal Verification RC Extraction IR-drop Analysis Linux Unix +13 more Show less

SystemVerilog C C++ Python RTL Computer Architecture Assembly Regression Frameworks Waveform Analysis Verification Methodology +5 more Show less

SystemVerilog C C++ Python RTL Computer Architecture Assembly Regression Frameworks Waveform Analysis Verification Methodology +5 more Show less

ASIC Physical Design Place and Route Floorplanning Clock and Power Distribution Global Signal Planning I/O Planning Hard IP Integration STA Design for Yield Multi Vt Database Management P&R Flows Physical Design Verification +9 more Show less

Physical Design Place and Route Floorplanning Clock and Power Distribution Timing Closure Electrical Verification STA Netlist to Tapeout SoC Design +4 more Show less

Physical Design Place and Route Floorplanning Clock and Power Distribution Timing Closure Electrical Verification STA Netlist to Tapeout Chip Architecture +4 more Show less

ASIC Integration Physical Design Floorplanning Place and Route RTL Clock and Power Distribution Global Signal Planning I/O Planning Cadence Synopsys Timing Verification Physical Design Verification Design for Yield Manufacturability multi Vt strategies +10 more Show less

ASIC Integration Physical Design Floorplanning Place and Route Clock and Power Distribution Global Signal Planning I/O Planning Cadence Synopsys Timing Verification Physical Design Verification RTL Design for Yield Manufacturability multi Vt strategies ESD Solutions +11 more Show less

ASIC Integration Physical Design Floorplanning Place and Route P&R Flows Timing Verification Physical Design Verification Clock and Power Distribution Global Signal Planning I/O Planning Hard IP Integration Mixed Signal Block Integration Design for Yield Manufacturability Multi Vt Strategies RTL Netlist to Tapeout +12 more Show less

ASIC Integration Physical Design Floorplanning Place and Route Clock and Power Distribution Global Signal Planning I/O Planning Hard IP Integration Timing Verification Physical Design Verification RTL Design for Yield Multi Vt GPU Architecture +9 more Show less

SystemVerilog C C++ Python RTL Computer Architecture Assembly Regression Frameworks Waveform Analysis Verification Methodology +5 more Show less

SystemVerilog C C++ Python RTL Assembly Computer Architecture Regression Frameworks Waveform Analysis Verification Methodology Coverage Convergence Embedded Programming +7 more Show less

ASIC Design Physical Design Place and Route Static Timing Analysis Clock Tree Synthesis Floorplanning Power Planning Signal Integrity Analysis Physical Verification DFT Low Power Design UPF Python Tcl Perl Shell Linux Unix Cadence Innovus Synopsys Fusion Compiler Synopsys PrimeTime RC Extraction ECO Implementation +18 more Show less