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ASIC Design System Verilog UVM DSP RTL MATLAB C C++ DFT Formal Verification DPI-C System C CMOS 5G NR LTE DVB-S2 Cadence Synopsys Mentor Graphics Low-Power Design Emulation +16 more Show less

Digital Layout CMOS Floorplanning Standard Cell Planning LVS DRC ERC CADENCE MENTOR GRAPHICS CALIBRE CSH PERL SKILL Memory Compiler Development Physical Design RC Delay Electromigration +12 more Show less

Digital Layout CMOS Floorplanning Standard Cell Planning LVS DRC ERC CALIBRE CADENCE MENTOR GRAPHICS CSH PERL SKILL Layout Automation Memory Compiler Development RC Delay Electromigration +12 more Show less

Digital Layout CMOS Floorplanning Standard Cell Planning Hierarchical Layout Assembly LVS DRC ERC CALIBRE CADENCE MENTOR GRAPHICS CSH PERL SKILL Layout Automation Memory Compiler Development RC Delay Electromigration +13 more Show less

Digital Layout CMOS Floorplanning Standard Cell Planning Hierarchical Layout Assembly LVS DRC ERC CALIBRE CADENCE MENTOR GRAPHICS CSH PERL SKILL Layout Automation Memory Compiler Development RC Delay Electromigration +13 more Show less

Matchmaking MMR Skill-rating systems Telemetry Live-service Scripting Technical Prototyping Anti-Cheat Analytics UX +5 more Show less

SystemVerilog Verilog Verilog-A/AMS Real Number Modeling RNM SPICE Xcelium Virtuoso RTL Development Mixed-Signal Simulation Digital Design Power Converters Verification Plans +8 more Show less

Circuit Design Cadence Virtuoso SPICE Python Perl Shell Static Timing Analysis EM and IR analysis Formal Functional Verification Layout Data Analysis +6 more Show less

Circuit Design RTL Layout Spice EM/IR Analysis Static Timing Analysis PnR Logic Synthesis Python Perl Tcl Make Power Gating DRC LVS Post-Silicon Characterization Hardware Security AI/ML +13 more Show less

SRAM Design Transistor-level Circuit Design Cadence Virtuoso FinFET Nanosheet Digital Circuit Design Layout Capture Logical Verification Silicon Testing Sense-amplifiers Self-timed Logic SRAM Compiler Development Codex Claude Code +9 more Show less

Mixed Signal Design CMOS Cadence Verilog Matlab PLL Transceivers CDR Data Converters High-Speed IO Timing Analysis Signal Integrity Power Integrity Silicon Characterization Lab Instrumentation Nanotime +11 more Show less

Signal Integrity PCB Design Cadence Allegro HFSS Sigrity Hspice PCIe LPDDR DDR GDDR MIPI HDMI USB TDR VNA Transmission Line Theory Electromagnetics PDN Constraints Manager +14 more Show less

Circuit Design Post-silicon Bringup Layout Support Silicon Validation Python Perl Tcl ATE Testing Hardware Security Voltage Regulation Data Analysis Synthesis +7 more Show less

Verilog SystemVerilog VHDL Python Perl SPICE HSPICE CMOS FinFET Cadence Synopsys EDA Tools Digital Circuit Design SRAM Timing and Delay Analysis Power Management Monte Carlo SerDes Object-Oriented Programming Operating Systems +15 more Show less

VLSI SPICE Perl Tcl Make DRC LVS RTL Logic Synthesis Place and Route ROM SRAM Flip Flops Level Shifters EM/IR Automation +11 more Show less

Power Converters Matlab Simulink Cadence SPICE Power Delivery Solutions Silicon EDA Load Modeling Design for Testing Silicon Validation +5 more Show less

Circuit Design Mixed-Signal Analog Digital Circuit Design Spice Simulation EM/IR Analysis Static Timing Analysis RTL Logic Synthesis Place and Route Design-for-Test (DFT) Perl Tcl Make ADC Op-Amp Transistor-level Analysis +11 more Show less

Circuit Design Cadence Virtuoso Python Perl SPICE Static Timing Analysis EM and IR Analysis Formal Verification Layout Data Analysis Memory Design +6 more Show less

Power Delivery Networks Power Management Matlab Simulink Simplis Spice verilogAMS Mixed-signal HSpice Spectre Primesim Cadence Virtuoso Allegro Ansys Sigrity Python Perl Tcl Skill S-parameters +15 more Show less

Verilog System Verilog RTL UVM Static Timing Analysis Synthesis P&R SerDes Ethernet InfiniBand PCIe USB Firmware Digital Design +9 more Show less