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Active Keyword: High-Speed Design Remove filter Clear all

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Senior Hardware Board Design Engineer, High-Speed

Cisco

Milpitas, CA 7 days ago $154,900–$225,300
Actively hiring Confirmed live today Posted this week High trust Competitive pay
ASIC PCB-design Schematic Capture Signal Integrity Power Integrity High-Speed Digital Design EMI/EMC Ethernet PCIe DDR4 DDR5 SerDes MDIO SPI I2C Cadence Concept/Design Entry Allegro HyperLynx ANSYS Keysight ADS Oscilloscope Protocol Analyzer Mixed-Signal Circuits
7+ yrs exp
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Next Gen High-Speed Memory and Cache Controller Design Engineer

Qualcomm

San Diego, CA 20 days ago $101,400–$152,200
Actively hiring Confirmed live today Trusted Below market
ASIC Design RTL LPDDR HBM DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Physical Design Micro-architecture ISA
3+ yrs exp
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ASIC/RTL Design Engineer for High-speed Interfaces

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400
Actively hiring Confirmed live today High trust Competitive pay
ASIC Design RTL Micro-architecture SerDes DDR Mixed-Signal IP VCS Fusion Compiler PrimeTime Power Compiler Spyglass DFT Static Timing Analysis Formal Verification Python Perl Digital Signal Processing PCIe USB UFS MIPI
7+ yrs exp
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Next-Gen High-Speed HBM LPDDR Memory Subsystem ASIC Digital Design Engineer

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400
Actively hiring Confirmed live today Trusted Competitive pay
ASIC Design RTL Coding Hardware Architecture LPDDR HBM NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis Digital Design ISA Architecture
4+ yrs exp
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Next-Gen High-Speed HBM LPDDR Memory Controller ASIC Digital Design Engineer

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400
Actively hiring Confirmed live today Trusted Competitive pay
ASIC Design RTL Coding Front-end Digital Design Hardware Architecture LPDDR HBM SRAM Cache Controller NoC x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis ISA Architecture
4+ yrs exp
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Next-Gen High-Speed Memory Subsystem ASIC Digital Design Engineer

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400
Actively hiring Confirmed live today Trusted Competitive pay
Verilog SystemVerilog ASIC Design RTL Design Synopsys Synthesis Low Power Design Python C C++ Computer Architecture Coverage-based Design Verification SOC Interconnects Memory Controllers micro architecture
4+ yrs exp
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High-Speed SerDes Design Engineer

Cisco

San Jose, CA 60 days ago $171,600–$245,000
Actively hiring Confirmed live today High trust Competitive pay
CMOS FinFET GAA Cadence (Virtuoso Spectre SpectreX Calibre Matlab AMS Power Integrity High Speed Serial Links OpAmps Electromigration Analysis IR Drop Analysis
8+ yrs exp Hybrid
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Principal Design Engineer, High-Speed Interconnect

Arm Holdings

Austin, TX 99 days ago $249,900–$338,100
Actively hiring Confirmed live today High trust Above market
SystemVerilog RTL PCIe CXL UALink AXI CHI ACE APB CDC RDC Formal Verification Synthesis Timing Analysis Waveform Debug Microarchitecture Cache Hierarchies Memory Systems High-Speed I/O Chiplets
8+ yrs exp Hybrid
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Senior Digital Design Engineer, High-Speed I/O and Photonics

Nvidia

Santa Clara, CA 141 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday High trust Competitive pay
Verilog System Verilog RTL UVM Static Timing Analysis Synthesis P&R SerDes Ethernet InfiniBand PCIe USB Firmware Digital Design
5+ yrs exp Hybrid
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