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Sr. ASIC DFT Engineer (Silicon)

SpaceX

Irvine, CA 2 days ago $125,000–$150,000
Actively hiring Posted this week Verified listing Below market
Siemens_Tessent Perl Python Tcl C++ IEEE_1500 IEEE_1687 In-System_Test_(IST) boundary_scan_IEEE_1149_1 Automated_Test_Equipment_(ATE) Teradyne Advantest Streaming_Scan_Network cell-aware_fault_models_ATPG
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Principal DFT Engineer (Silicon Engineering)

SpaceX

Sunnyvale, CA 2 days ago $210,000–$295,000
Actively hiring Posted this week Verified listing Above market
Perl Python Tcl C++ Siemens_Tessent UPF Verilog SystemVerilog ATE_testers DFT ATPG RTL SDF_annotated_gate_level_simulations
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Principal DFT Engineer (Silicon Engineering)

SpaceX

Irvine, CA 2 days ago $200,000–$285,000
Actively hiring Posted this week Verified listing Above market
Siemens_Tessent Perl Python Tcl C++ Verilog SystemVerilog UPF DRC ATE_testers ASIC_design RTL_simulation Gate_level_simulation SDF_annotated_simulations Design_for_Test(DFT) Scan_insertion ATPG_tools Pattern_compression Hierarchical_test_flows
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DFT Engineer - New College Grad

Nvidia

Santa Clara, CA 25 days ago $116,000–$189,750
Actively hiring Competitive pay
Perl Python Tcl DFT BIST ATPG fault simulation RTL design STA place-n-route power analysis Silicon debug ATE pattern formats failure processing test program development
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CPU DFT Engineer

Qualcomm

Santa Clara, CA 29 days ago $142,200–$213,400
Actively hiring Competitive pay
Verilog VHDL Mentor Tessent tools TCL Perl Python Shell scripting JTAG ATPG IEEE 1500 Standard MBIST LBIST SOC level verification Test compression software
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DFT Engineer

Broadcom

San Jose, CA 37 days ago $120,000–$192,000
Actively hiring Verified listing Below market
TetraMax Fastscan Verilog IEEE1687 IJTAG ICL PDL Python Statistical_process_control ATE Serdes DDR PCIE ENET CXL I/O_BIST DFT Pattern_generation Test_vector_debugging
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ASIC Engineering Technical Lead - DFT

Cisco

San Jose, CA 38 days ago $183,800–$263,600
Actively hiring Above market
Python Tcl C++ Siemens_Tessent Synopsys RTL Verilog System_Verilog DFT ATPG SDF Scan_Insertion Memory_BIST Logic_BIST ATE_testers
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ASIC DFT Engineer

Broadcom

San Jose, CA 39 days ago $141,300–$226,000
Actively hiring Verified listing Competitive pay
TetraMax Fastscan Verilog IEEE1687 IJTAG ICL PDL Python Statistical_Process_Control ATE Serdes DDR PCIE ENET CXL I/O_BIST DFT Testbench_Generation Simulation Debugging Root_Cause_Analysis
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ASIC DFT Engineer

Broadcom

San Jose, CA 40 days ago $141,300–$226,000
Actively hiring Verified listing Competitive pay
DFT Scan MBIST TAP LBIST IO SerDes Pattern_Generation ATPG TetraMax Fastscan Verilog IEEE1149.1 IEEE1149.6 TestKompress Mentor_TestKompress Boundary_Scan IEEE1687 IJTAG ICL PDL Test-STA Analog_Design Digital_Circuit_Design Si_Processing Logical_Synthesis Physical_Synthesis Statistical_Process_Control ATE DDR PCIE ENET CXL_IOBIST Tessent_SSN
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DFT Engineer

Broadcom

San Jose, CA 43 days ago $141,300–$226,000
Actively hiring Verified listing Competitive pay
TCL PERL RUBY PYTHON C++ Verilog IEEE1687 IJTAG ICL PDL DFT ATE Serdes DDR PCIE ENET CXL IOBIST TetraMax Fastscan
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ASIC DFT Engineer

Broadcom

Fort Collins, CO 106 days ago $108,000–$172,800
Actively hiring Verified listing Below market
TCL PERL RUBY Python C++ Verilog IEEE1687 IJTAG ICL PDL TetraMax Fastscan ATE Serdes DDR PCIE ENET CXL I/O BIST Statistical Process Control
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ASIC DFT Engineer

Broadcom

Fort Collins, CO 106 days ago $108,000–$172,800
Actively hiring Verified listing Below market
TCL PERL RUBY Python C++ Verilog IEEE1687 IJTAG ICL PDL TetraMax Fastscan ATE Serdes DDR PCIE ENET CXL I/O BIST Statistical Process Control
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