DFT Engineer

Broadcom

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$120,000–$192,000 / yr
Posted
37 days ago
Closes
Oct 27, 2026

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $179k
This role $156k
$108k most similar roles pay here $230k

This role pays less than 67% of similar roles. Most pay $150,000–$208,000 — the shaded band above. At the midpoint, this role pays about $156k versus about $179k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 61 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 60 roles with salary data.

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At a glance

TL;DR · DFT Engineer

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Broadcom's ASIC Product Division in San Jose, California, seeks a senior DFT engineer to join their dynamic team, responsible for defining and implementing comprehensive DFT programs from specification through production release. The role involves working on SoC DFT activities such as architecture design, test insertion, pattern generation, coverage improvement, post-silicon debug, and yield enhancement in collaboration with Physical Design and STA teams. Key responsibilities include understanding feature requirements, generating and verifying test vectors, supporting ATE bring-up, and driving yield improvements through innovative solutions and automation. Ideal candidates possess a strong background in Verilog coding, IEE1687 standards, statistical process control, and project management, along with experience in TetraMax and Fastscan for logic BIST design. Additional knowledge of Serdes, DDR, PCIE, ENET, CXL IOBIST verification is beneficial.

Skills

TetraMax Fastscan Verilog IEEE1687 IJTAG ICL PDL Python Statistical_process_control ATE Serdes DDR PCIE ENET CXL I/O_BIST DFT Pattern_generation Test_vector_debugging

What you'll do

  • Define DFT specifications for ASICs based on Broadcom and customer requirements.
  • Generate and verify test vectors at chip level before tape release.
  • Validate and debug test vectors on ATE during silicon bring-up phase.
  • Assist in silicon failure analysis, diagnostics, and yield improvement efforts.
  • Innovate new DFT solutions to address testability issues in advanced nodes.

What we're looking for

  • 8+ years of experience in DFT or related field (BS) or 6+ years (MS)
  • Expertise in Logic BIST design and debugging using TetraMax, Fastscan
  • Proficient in Verilog coding, testbench generation, and simulation
  • Strong knowledge of IEE1687, IJTAG, ICL, PDL standards
  • Excellent problem-solving, debug, root cause analysis, and communication skills
  • Experience with statistical process control and data analysis for yield improvement

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