Principal DFT Engineer (Silicon Engineering)

SpaceX

Quick summary

Work type
On-site
Location
Irvine, CA
Salary
$200,000–$285,000 / yr
Posted
today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $195k
This role $242k
$145k most similar roles pay here $300k

This role pays more than 88% of similar roles. Most pay $168,500–$222,000 — the shaded band above. At the midpoint, this role pays about $242k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

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At a glance

TL;DR · Principal DFT Engineer (Silicon Engineering)

The Principal DFT Engineer role at Silicon Engineering in Irvine, CA, is a senior-level position responsible for leading the implementation and optimization of Design for Test (DFT) architectures. This includes managing scan insertion, compression/decompression logic, memory BIST, and logic BIST using Siemens Tessent tools, as well as generating test patterns and providing post-silicon testing support. The candidate will work closely with design teams to ensure DFT fabrics are integrated and verified within subsystems, leveraging Verilog/SystemVerilog for block implementation and integration. Essential skills include experience with RTL debugging, UPF, formal verification, and ATE testers, alongside proficiency in programming languages such as Perl, Python, Tcl, or C+. The role requires deep expertise in advanced silicon processes and high-speed, low-power technology nodes, contributing to the development of cutting-edge semiconductor products.

What you'll do

  • Lead implementation and optimization of DFT architectures using Siemens Tessent tools.
  • Own ATPG tools and methodologies, generating patterns for various fault models.
  • Evaluate design readiness for scan insertion through RTL and physical design Scan DRC tools.
  • Integrate and verify Design for Test (DFT) fabrics and IP within Subsystems.
  • Develop test scripts and automate processes using programming languages like Perl or Python.

What we're looking for

  • 10+ years of experience in ASIC design and DFT setup, integration, validation
  • Leadership experience driving SOC DFT execution from concept through tapeout
  • Expertise in RTL for understanding and debugging connectivity issues related to DFT
  • Familiarity with UPF, formal verification, and DRC rule checking
  • Experience with advanced silicon processes and technology nodes for high-speed, low-power designs
  • Strong implementation or integration of design blocks using Verilog/SystemVerilog
  • Knowledge of ATE testers and collaboration with test teams

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