Principal DFT Engineer (Silicon Engineering)

SpaceX

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $210,000–$295,000 / yr
Posted: today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $195k

This role $252k

$144k most similar roles pay here $311k

This role pays more than 90% of similar roles. Most pay $168,500–$222,000 — the shaded band above. At the midpoint, this role pays about $252k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

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At a glance

TL;DR · Principal DFT Engineer (Silicon Engineering)

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The Principal DFT Engineer role at Silicon Engineering in Sunnyvale, CA is a senior position responsible for leading the implementation and optimization of Design for Test (DFT) architectures. This includes managing scan insertion, compression/decompression logic, memory BIST, and logic BIST using Siemens Tessent tools, as well as generating test patterns for various fault models and providing post-silicon testing support. The candidate will also evaluate design readiness through RTL and physical design DRC tools, integrate DFT fabrics into subsystems, and run gate-level simulations. Key skills required include extensive experience with ASICs, scan insertion, UPF, formal verification, and advanced silicon process nodes. Proficiency in Verilog/SystemVerilog, Perl, Python, Tcl, or C+ is essential for developing test scripts and automating processes.

Skills

Perl Python Tcl C++ Siemens_Tessent UPF Verilog SystemVerilog ATE_testers DFT ATPG RTL SDF_annotated_gate_level_simulations

What you'll do

Lead implementation and optimization of DFT architectures using Siemens Tessent tools.
Own ATPG methodologies, generating patterns for various fault models with focus on compression and diagnosis.
Evaluate design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools.
Integrate and verify DFT fabrics and IP within Subsystems during the design process.
Develop test scripts and automate processes using programming languages like Perl, Python, or Tcl.

What we're looking for

10+ years of experience in ASIC design and DFT setup, integration, validation
Leadership experience driving SOC DFT execution from concept through tapeout
Expertise in RTL for understanding and debugging connectivity issues related to DFT
Experience with UPF, formal verification, and DRC rule checking
Strong implementation or integration skills using Verilog/SystemVerilog
Familiarity with advanced silicon process nodes and ATE testers

Remote

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