ASIC DFT Engineer

Broadcom

Quick summary

Work type
On-site
Location
Fort Collins, CO
Salary
$108,000–$172,800 / yr
Posted
106 days ago
Closes
Aug 19, 2026

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $188k
This role $140k
$95k most similar roles pay here $233k

This role pays less than 88% of similar roles. Most pay $158,850–$216,250 — the shaded band above. At the midpoint, this role pays about $140k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 61 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 60 roles with salary data.

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At a glance

TL;DR · ASIC DFT Engineer

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Broadcom's ASIC Product Division is hiring a DFT Engineer at its Fort Collins, Colorado Development Center to work on various phases of SoC DFT activities including architecture, test insertion, pattern generation, coverage improvement, post-silicon debug, and yield enhancement. The role involves collaborating with Physical Design & STA teams for timing closure and requires proficiency in scripting languages such as TCL, PERL, RUBY, PYTHON, or C++. Key responsibilities include defining DFT specifications based on Broadcom and customer requirements, validating HBM and Die2Die IPs at the ASIC level, generating test vectors, debugging issues during silicon bring-up, and innovating solutions for advanced node challenges. Candidates should have experience with Logic BIST design, Verilog coding, IEE1687 standards, statistical process control, and ATE validation, along with strong problem-solving and communication skills.

Skills

TCL PERL RUBY Python C++ Verilog IEEE1687 IJTAG ICL PDL TetraMax Fastscan ATE Serdes DDR PCIE ENET CXL I/O BIST Statistical Process Control

What you'll do

  • Define DFT specifications to meet Broadcom and customer requirements.
  • Verify and validate HBM & Die2Die IP's at the ASIC level.
  • Generate, verify, and debug test vectors before tape release.
  • Validate and debug test vectors on ATE during silicon bring-up phase.
  • Assist with failure analysis and yield improvement efforts post-silicon.

What we're looking for

  • Extensive DFT architecture, test insertion, pattern generation, and coverage improvement expertise.
  • Proficiency in scripting languages (TCL, PERL, RUBY, PYTHON, C++) for automation tasks.
  • Logic BIST design and debug experience using TetraMax, Fastscan tools.
  • Strong background in IEE1687, IJTAG, ICL, PDL standards and statistical process control techniques.
  • Experience validating and debugging test vectors on ATE during silicon bring-up phase.
  • Ability to innovate DFT solutions for advanced nodes (3nm and beyond) and automate flows.

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