DFT Engineer

Broadcom

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$141,300–$226,000 / yr
Posted
43 days ago
Closes
Oct 21, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $179k
This role $184k
$125k most similar roles pay here $237k

This role pays more than 60% of similar roles. Most pay $150,000–$208,000 — the shaded band above. At the midpoint, this role pays about $184k versus about $179k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 61 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 60 roles with salary data.

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At a glance

TL;DR · DFT Engineer

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Broadcom's ASIC Product Division is hiring a Principal DFT Engineer to work on various phases of SoC DFT activities, including architecture, test insertion, pattern generation, coverage improvement, post-silicon debug, and yield enhancement. The role involves collaborating with Physical Design & STA teams for timing closure and requires expertise in scripting languages such as TCL, PERL, RUBY, PYTHON, or C++. Key responsibilities include defining DFT specifications based on Broadcom and customer requirements, generating and debugging test vectors, validating tests during silicon bring-up, and innovating solutions to address testability issues at 7nm and beyond. The ideal candidate has extensive experience in Verilog coding, testbench generation, simulation, IEE1687, IJTAG, ICL, PDL, ATE work, and Serdes, DDR, PCIE, ENET, CXL IOBIST verification and silicon debug.

Skills

TCL PERL RUBY PYTHON C++ Verilog IEEE1687 IJTAG ICL PDL DFT ATE Serdes DDR PCIE ENET CXL IOBIST TetraMax Fastscan

What you'll do

  • Define DFT specifications based on Broadcom and customer requirements.
  • Generate, verify, and debug test vectors before tape release.
  • Validate and debug test vectors during silicon bring-up phase.
  • Assist in failure analysis and yield improvement efforts post-silicon.
  • Innovate new DFT solutions for advanced node challenges (7nm and beyond).
  • Automate DFT and test vector generation flows to enhance efficiency.

What we're looking for

  • At least 10 years of experience in DFT for ASIC design (Masters required)
  • Expertise in Verilog, testbench generation, simulation, and IEE1687 standards
  • Proficient in TCL, PERL, RUBY, PYTHON, C++ or similar scripting languages
  • Strong problem-solving skills with experience in ATE validation and debugging
  • Experience in Serdes, DDR, PCIE, ENET, CXL IOBIST verification preferred
  • Ability to innovate DFT solutions for advanced nodes (7nm and beyond)

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