ASIC DFT Engineer

Broadcom

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$141,300–$226,000 / yr
Posted
40 days ago
Closes
Oct 24, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $187k
This role $184k
$131k most similar roles pay here $236k

This role pays more than 53% of similar roles. Most pay $158,275–$216,250 — the shaded band above. At the midpoint, this role pays about $184k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 61 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 60 roles with salary data.

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At a glance

TL;DR · ASIC DFT Engineer

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Broadcom's ASIC Product Division in San Jose seeks an experienced DFT Engineer to join their dynamic team, focusing on defining and implementing comprehensive DFT specifications for complex SoC designs. This role involves collaborating with Physical Design and STA teams to ensure timing closure while working on various phases of DFT activities including architecture, test insertion, pattern generation, coverage improvement, post-silicon debug, and yield enhancement. The ideal candidate will have a strong background in DFT technologies such as Scan, MBIST, TAP, LBIST, IO, SerDes integration, and ATPG vector generation using tools like Mentor TestKompress and TetraMax. Additionally, proficiency in Verilog coding, testbench creation, and simulation is essential, along with knowledge of IEEE standards including 1149.1 and 1687. The position requires expertise in analog and digital circuit design, silicon processing, and statistical process control to drive yield improvements, as well as the ability to manage projects across multiple stakeholders.

Skills

DFT Scan MBIST TAP LBIST IO SerDes Pattern_Generation ATPG TetraMax Fastscan Verilog IEEE1149.1 IEEE1149.6 TestKompress Mentor_TestKompress Boundary_Scan IEEE1687 IJTAG ICL PDL Test-STA Analog_Design Digital_Circuit_Design Si_Processing Logical_Synthesis Physical_Synthesis Statistical_Process_Control ATE DDR PCIE ENET CXL_IOBIST Tessent_SSN

What you'll do

  • Define DFT specifications based on Broadcom and customer requirements.
  • Implement DFT features including scan, MBIST, TAP, LBIST, IO, SerDes integration.
  • Generate and verify chip-level test patterns for rapid ATE bring-up.
  • Collaborate with STA engineers to ensure DFT mode timing closure.
  • Debug and improve yield through silicon failure analysis and diagnostics.
  • Innovate new DFT solutions for advanced nodes like 3nm and beyond.

What we're looking for

  • 12+ years of DFT experience or equivalent education in related field.
  • Strong background in Scan Insertion, scan compression, and Logic BIST design.
  • Proficiency in ATPG vector generation, simulation, and debugging tools.
  • Knowledge of IEEE standards (1149.1, 1687) and memory BIST insertion.
  • Experience working on ATE with silicon failure analysis and yield improvement.
  • Solid understanding of analog and digital circuit design fundamentals.
  • Excellent problem-solving skills and ability to work in a multi-disciplined team.

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