DFT Engineer

What you'll do

• Execute end-to-end DFT for sophisticated chips from methodology development to post-silicon lifecycle support.
• Partner with EDA tool vendors to develop new capabilities that meet specific hardware requirements.
• Collaborate with internal CAD teams to drive efficiency through automated workflows.
• Deliver scan features across all product segments in coordination with VLSI and Operations teams.
• Mentor junior engineers on test designs, cost trade-offs, and quality standards.
• Define scan test plans, BIST for memories and IOs, fault modeling, and ATPG.
• Verify and validate test patterns and logic on multi-million gate designs using vendor tools.
• Perform silicon debug and bring-up on ATE including pattern formats and test program development.

What we're looking for

• Pursuing a Master's degree, PhD, or equivalent experience is required.
• Knowledge of scan test plans, BIST for memories and IOs, fault modeling, ATPG, and fault simulation is required.
• Analytical skills in verification and validation of test patterns and logic on multi-million gate designs are required.
• Experience with RTL, clock design, STA, place-and-route, and power management is required.
• Experience in silicon debug and bring-up on ATE with knowledge of pattern formats and failure processing is required.
• Proficiency in developing test programs and understanding of test program development is required.
• Strong programming and scripting skills in Perl, Python, or Tcl are desired.