DFT Engineer, New College Grad

Nvidia

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $116,000–$189,750 / yr
Employment: Full-time
Posted: 128 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $176k

This role $153k

$104k $228k

below market most similar roles pay here above market

This role pays less than 61% of similar roles. Most pay $135,437–$216,250 — the blue band above. At the midpoint, this role pays about $153k versus about $176k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1673 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1080 roles with salary data.

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At a glance

TL;DR · DFT Engineer, New College Grad

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The DFT Engineer - New College Grad will join the Design-for-Test Engineering team to work on groundbreaking innovations for sophisticated semiconductor chips. This role involves end-to-end DFT responsibilities, including methodology, deployment, and post-silicon lifecycle support. You will partner with EDA tool vendors to develop new capabilities, collaborate with internal CAD teams to drive efficiency via automations, and work with VLSI and Operations teams to deliver scan features across all product segments. Key tasks include defining scan test plans, BIST for memories and IOs, fault modeling, ATPG, and fault simulation. Required skills include analytical verification of test patterns on multi-million gate designs, knowledge of RTL, clocks, STA, and place-n-route. Proficiency in Perl, Python, or Tcl scripting is desired for silicon debug and ATE test program development.

Skills

DFT ATPG BIST Fault Modeling Fault Simulation Scan Test Plans Silicon Debug ATE RTL STA Python Perl Tcl CAD Post-Silicon Validation

What you'll do

Execute end-to-end DFT for sophisticated chips from methodology to post-silicon lifecycle support.
Partner with EDA tool vendors to develop new capabilities for specific NVIDIA requirements.
Work with internal CAD teams to drive efficiency through automation.
Deliver scan features across all product segments in coordination with VLSI and Operations teams.
Mentor junior engineers on test designs and trade-offs regarding cost and quality.
Define scan test plans, BIST for memories and IOs, fault modeling, and ATPG.
Perform verification and validation of test patterns and logic on multi-million gate designs.
Conduct silicon debug and bring-up on ATE including failure processing and test program development.

What we're looking for

Pursue a MS or PhD or have equivalent experience.
Possess knowledge in defining scan test plans, BIST for memories and IOs, fault modeling, ATPG, and fault simulation.
Demonstrate excellent analytical skills in verification and validation of test patterns and logic on multi-million gate designs.
Have good exposure to RTL and clocks design, STA, place-n-route, and power.
Have experience in silicon debug and bring-up on the ATE with an understanding of pattern formats and failure processing.
Possess strong programming and scripting skills in Perl, Python, or Tcl (preferred).

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