Join NVIDIA’s Design-for-Test Engineering team as a DFT Engineer and contribute to groundbreaking innovations by crafting creative solutions for DFT architecture, verification, and post-silicon validation on cutting-edge semiconductor chips. In this role, you will collaborate with EDA tool vendors to develop new capabilities, work closely with internal CAD teams to enhance efficiency through automation, and support the VLSI and Operations teams in delivering scan features across all product segments. Additionally, you will mentor junior engineers on test design trade-offs involving cost and quality. Ideal candidates possess a BSEE or MSEE (or equivalent experience) and expertise in defining scan test plans, fault modeling, ATPG, and fault simulation using vendor tools. Strong analytical skills for verification and validation of complex designs are essential, along with exposure to multiple domains such as RTL design, STA, place-n-route, and power management. Experience in silicon debug and bring-up on ATE systems is a plus, alongside proficiency in Perl, Python, or Tcl scripting.
Skills
Perl
Python
Tcl
DFT
BIST
ATPG
fault simulation
RTL design
STA
place-n-route
power analysis
Silicon debug
ATE pattern formats
failure processing
test program development
What you'll do
Develop end-to-end DFT methodologies for complex semiconductor chips.
Collaborate with EDA vendors to create new capabilities for NVIDIA requirements.
Mentor junior engineers on test design and trade-offs related to cost and quality.
Work closely with VLSI teams to implement scan features across all product segments.
Conduct verification and validation of test patterns using advanced vendor tools.
What we're looking for
Bachelor’s or Master’s degree in Electrical Engineering with relevant experience.
Expertise in defining scan test plans and BIST for memories and IOs.
Proficient in fault modeling, ATPG, and fault simulation using vendor tools.
Strong analytical skills for verification and validation of complex designs.
Experience in silicon debug and bring-up on ATE systems.
Good understanding of multiple domains including RTL design and power management.
Market check
Salary context
This
$116,000–$189,750
range sits above
50%
of similar postings on FindRole.
Peer median band
$116,500–$198,000
Median floor and ceiling across peers.
Typical midpoint (25–75%)
$135,000–$177,387
Middle half of comparable postings.
Based on 240 comparable postings.*
* 240 is the maximum number of comparable postings sampled.
Employer
About Nvidia
Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing
Nvidia currently has
801 open roles
on FindRole.
Listed pay typically runs
$184,000–$287,500
across 797 roles with salary data.
Us, Ca, Santa Clara, US86 days ago
$136,000–$218,500
Perl
Python
Tcl
DFT
BIST
ATPG
fault simulation
vendor tools
RTL
STA
place-n-route
power management
Silicon debug
ATE
pattern formats
failure processing
test program development