ASIC DFT Engineer

Broadcom

Quick summary

Work type
On-site
Location
Fort Collins, CO
Salary
$108,000–$172,800 / yr
Posted
106 days ago
Closes
Aug 19, 2026

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $188k
This role $140k
$95k most similar roles pay here $233k

This role pays less than 88% of similar roles. Most pay $158,850–$216,250 — the shaded band above. At the midpoint, this role pays about $140k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 61 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 60 roles with salary data.

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At a glance

TL;DR · ASIC DFT Engineer

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Broadcom's ASIC Product Division is hiring a DFT Engineer for its Fort Collins, Colorado Development Center. This senior-level position involves working on various phases of SoC DFT activities including architecture definition, test insertion, pattern generation, coverage improvement, post-silicon debug, and yield enhancement to meet stringent product metrics. The role requires coding in languages such as TCL, PERL, RUBY, PYTHON, or C++ for automation tasks. Key responsibilities include defining DFT specifications based on Broadcom and customer requirements, ATPG and verification at the chip level, rapid bring-up at ATE, and RMA support. Candidates should have experience with Logic BIST design, Verilog coding, testbench generation, IEE1687, IJTAG, and statistical process control techniques to drive yield improvements. Strong problem-solving skills and project management capabilities are essential for success in this role.

Skills

TCL PERL RUBY Python C++ Verilog IEEE1687 IJTAG ICL PDL TetraMax Fastscan ATE Serdes DDR PCIE ENET CXL I/O BIST Statistical Process Control

What you'll do

  • Define DFT specifications to meet Broadcom and customer requirements.
  • Generate, verify, and debug test vectors before tape release for ASICs.
  • Validate and debug test vectors on ATE during silicon bring-up phase.
  • Assist in silicon failure analysis and yield improvement efforts.
  • Innovate new DFT solutions to address testability issues in advanced nodes.

What we're looking for

  • Extensive DFT architecture, test insertion, verification, and pattern generation experience.
  • Proficiency in scripting languages (TCL, PERL, RUBY, PYTHON, C++) for automation.
  • Strong background in IEE1687, IJTAG, ICL, PDL, and logic BIST design/debugging.
  • Experience with ATE validation, debugging, and silicon failure analysis.
  • Ability to innovate DFT solutions and automate test vector generation flows.

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