Browse tech roles

Basic role filtering by workplace, salary floor, and post age. For full AI matching and advanced filtering upload your resume using AI Match.

Active Keyword: ASIC Physical Design Engineer Remove filter Clear all

8 of up to 20 (filtered)

AI-Driven ASIC Physical Design Principal Engineer

Cisco

Remote (San Jose, CA) 18 days ago $250,600–$362,600
Actively hiring Confirmed live 2 days ago High trust Above market
Python Claude Innovus ICC2 Calibre Tcl Docker OpenAI API Pinecone Weaviate RAG LLM MLPD STA DRC EDA Tools Vector Databases
10+ yrs exp Remote
Save

ASIC Physical Design Engineer, Netlisting

Nvidia

Santa Clara, CA +1 29 days ago $116,000–$189,750
Actively hiring Confirmed live 2 days ago High trust Below market
ASIC Physical Design Logic Synthesis Formal Verification Equivalence Checking RTL Timing Closure Clock Domain Crossing MTBF Analysis Synopsys Cadence Python TCL Perl Make EDA Tools Netlisting ECO Generation
Save

Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

Nvidia

Santa Clara, CA +1 32 days ago $136,000–$218,500
Actively hiring Confirmed live 2 days ago High trust Competitive pay
Physical Design Synthesis Timing Analysis Floor-planning Verilog ASIC Design Flow RTL Design Verification DFT ECO High-frequency Design Micro-architecture
5+ yrs exp
Save

Senior ASIC Physical Design Engineer, Netlisting

Nvidia

Santa Clara, CA +1 37 days ago $136,000–$218,500
Actively hiring Confirmed live 2 days ago High trust Competitive pay
ASIC Physical Design Logic Synthesis Static Timing Analysis (STA) Equivalence Checking DFT Python TCL Perl Make EDA Tools Netlist Quality Check Timing Closure ECO Generation Hardware Architecture
5+ yrs exp Hybrid
Save

ASIC Physical Design and Timing Engineer

Nvidia

Santa Clara, CA 51 days ago $116,000–$189,750
Actively hiring Confirmed live 2 days ago High trust Below market
Static Timing Analysis STA ASIC Physical Design Synthesis Floor-planning CTS Routing Equivalence Checking Timing Constraints Power Convergence ECO AI LLM
Save

Senior SOC/ASIC Physical Design Engineer

SpaceX

Irvine, CA 108 days ago $165,000–$260,000
Actively hiring Confirmed live yesterday Low trust Competitive pay
ASIC SOC Physical Design RTL2GDSII Static Timing Analysis (STA) EDA Tools Python TCL Perl Bash Makefile DFT Scan MBIST LBIST FinFET CMOS Floorplanning Place and Route Synthesis
5+ yrs exp
Save

Senior SOC/ASIC Physical Design Engineer

SpaceX

Sunnyvale, CA 108 days ago $175,000–$280,000
Actively hiring Confirmed live 2 days ago Low trust Above market
ASIC Physical Design RTL2GDSII STA EDA Tools Python TCL Perl Bash Makefile DFT Scan MBIST LBIST FinFET CMOS Floorplanning Place and Route Synthesis Electromigration
5+ yrs exp
Save

Senior SOC/ASIC Physical Design Engineer

SpaceX

Austin, TX 108 days ago
Actively hiring Confirmed live 2 days ago Low trust
ASIC SOC Physical Design RTL2GDSII Static Timing Analysis STA Floorplanning Place and Route DFT Scan MBIST LBIST FinFET CMOS Python TCL Perl Bash Makefile EDA Tools
5+ yrs exp
Save