ASIC Physical Design and Timing Engineer

Nvidia

Confirmed live today Trusted

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$116,000–$189,750 / yr
Employment
Full-time
Posted
97 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $185k
This role $153k
$104k $231k
below market most similar roles pay here above market

This role pays less than 73% of similar roles. Most pay $152,875–$216,250 — the blue band above. At the midpoint, this role pays about $153k versus about $185k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · ASIC Physical Design and Timing Engineer

Role Posting Log in to save

JOB TITLE: ASIC Physical Design and Timing Engineer - New College Grad 2026 The ASIC Physical Design and Timing Engineer - New College Grad 2026 joins a dynamic team to drive physical design and timing analysis for GPUs, CPUs, DPUs, and SoCs. This role involves performing analysis and closure at the block, cluster, and full chip levels. Key responsibilities include driving frontend and backend implementation tasks such as synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation. Candidates must demonstrate proficiency in Timing and Static Timing Analysis (STA), including full-chip or sub-chip timing convergence and constraints management. The role requires expertise with industry standard EDA and timing convergence tools. The work focuses on solving complex hardware challenges within deep sub-micron process nodes for high-performance computing components.

Skills

Static Timing Analysis (STA) Physical Design Synthesis Floorplanning Placement Routing Equivalence Checking Timing Convergence ECO Deep Learning LLM

What you'll do

  • Drive physical design and timing analysis for GPUs, CPUs, DPUs, and SoCs.
  • Perform timing closure at the block, cluster, and full chip levels.
  • Manage frontend and backend implementation including synthesis and equivalence checking.
  • Execute floor-planning and manage timing constraints for complex designs.
  • Achieve timing and power convergence across various hardware components.
  • Implement Engineering Change Orders (ECO) to resolve design issues.
  • Utilize industry-standard EDA and timing convergence tools to optimize performance.

What we're looking for

  • Master's degree or higher in Electrical or Computer Engineering (or equivalent experience).
  • Proficiency in Timing and Static Timing Analysis (STA).
  • Hands-on experience in full-chip/sub-chip STA and timing convergence.
  • Experience in timing constraints generation and management.
  • Expertise with industry standard EDA and timing convergence tools.
  • Proven experience in timing convergence for ASICs, CPUs, GPUs or Network processors (preferred).
  • Knowledge of deep sub-micron process nodes (preferred).
  • Proficiency in AI/LLM and programming languages (preferred).
  • Experience in physical design and optimization such as synthesis, floorplanning, placement, CTS, routing, and power (preferred).

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