ASIC Physical Design and Timing Engineer

Nvidia

Confirmed live 2 days ago High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $116,000–$189,750 / yr
Posted: 51 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $185k

This role $153k

$104k most similar roles pay here $231k

This role pays less than 75% of similar roles. Most pay $153,100–$216,250 — the shaded band above. At the midpoint, this role pays about $153k versus about $185k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · ASIC Physical Design and Timing Engineer

Role Posting Log in to save

As an ASIC Physical Design and Timing Engineer - New College Grad 2026, you will join a dynamic team to drive physical design and timing analysis for GPUs, CPUs, DPUs, and SoCs at the block, cluster, and full chip levels. Your daily responsibilities include driving frontend and backend implementation tasks such as synthesis, equivalence checking, floor-planning, timing constraints, power convergence, and ECO implementation within a cross-functional environment. To succeed in this role, you must possess a master's degree or higher in Electrical or Computer Engineering and demonstrate proficiency in Timing and Static Timing Analysis (STA). You will utilize industry standard EDA and timing convergence tools to manage full-chip or sub-chip STA and timing constraints. The work focuses on the technical challenges of physical design and optimization for complex integrated circuits across various hardware architectures.

Skills

Static Timing Analysis STA ASIC Physical Design Synthesis Floor-planning CTS Routing Equivalence Checking Timing Constraints Power Convergence ECO AI LLM

What you'll do

Drive physical design and timing analysis for GPUs, CPUs, DPUs, and SoCs at various levels of integration.
Perform timing closure for block level, cluster level, and full chip designs.
Manage frontend and backend implementation including synthesis and equivalence checking.
Develop and manage timing constraints to ensure successful hardware execution.
Execute timing and power convergence across complex integrated circuits.
Implement Engineering Change Orders (ECO) to resolve design issues.
Utilize industry-standard EDA tools to achieve timing convergence for ASIC designs.

What we're looking for

Master's degree or higher in Electrical Engineering, Computer Engineering, or equivalent experience.
Proficiency in Timing and Static Timing Analysis (STA).
Hands-on experience in full-chip/sub-chip STA and timing convergence.
Experience with timing constraints generation and management.
Expertise with industry standard EDA and timing convergence tools.
Proven experience in timing convergence for ASICs, CPUs, GPUs, or Network processors.
Knowledge of deep sub-micron process nodes.
Proficiency in AI/LLM and programming languages.

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