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Active Keyword: ASIC Physical Design Remove filter Clear all

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Senior ASIC Physical Design Engineer, Netlisting

Nvidia

Santa Clara, CA +1 11 days ago $136,000–$218,500
Actively hiring Confirmed live today High trust Competitive pay
ASIC Physical Design Logic Synthesis Static Timing Analysis (STA) Logic Equivalence Checking MTBF Analysis Timing Closure DFT Python Perl TCL Make EDA Tools ECO Generation
5+ yrs exp Hybrid
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ASIC Physical Design Engineer

Cisco

San Jose, CA +2 19 days ago
Actively hiring Confirmed live today High trust
RTL-to-GDSII Physical Design Static Timing Analysis STA Innovus Tempus Primetime Redhawk Voltus Calibre Python TCL Perl Clock Tree Synthesis CTS Power Integrity Floorplanning Place and Route Equivalence Checks
6+ yrs exp
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ASIC Physical Design Engineer II

Cisco

San Jose, CA 26 days ago $125,700–$203,100
Actively hiring Confirmed live today High trust Below market
ASIC Physical Design RTL-to-GDSII Floor Planning Place and Route Clock Tree Synthesis Static Timing Analysis STA PrimeTime Cadence Innovus Synopsys ICC2 Synopsys Design Compiler Mentor Calibre DRC LVS Python Tcl Perl Logic Synthesis Timing ECO
2+ yrs exp Hybrid
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AI-Driven ASIC Physical Design Principal Engineer

Cisco

San Jose, CA 64 days ago
Actively hiring Confirmed live today High trust
Python ASIC EDA Tools Innovus ICC2 Calibre Tcl Docker RAG LLM Pinecone Weaviate OpenAI API GPT-4o MLPD RTL2GDSII Tempus Primetime Redhawk Voltus Pegasus
10+ yrs exp Hybrid
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ASIC Physical Design Engineer, Netlisting

Nvidia

Santa Clara, CA +1 75 days ago $116,000–$189,750
Actively hiring Confirmed live today High trust Below market
ASIC Physical Design Logic Equivalence Checking Formal Verification Logic Synthesis Clock Domain Crossing MTBF Analysis ECO Generation Python Perl TCL Make Synopsys Cadence Hardware Architecture Timing Closure
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Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

Nvidia

Santa Clara, CA +1 78 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday High trust Competitive pay
Physical Design ASIC Design Flow Synthesis Timing Analysis Verilog RTL Design DFT ECO Floor-planning High-Frequency Design Micro-architecture
5+ yrs exp
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ASIC Physical Design and Timing Engineer

Nvidia

Santa Clara, CA 97 days ago $116,000–$189,750
Actively hiring Confirmed live today Trusted Below market
Static Timing Analysis (STA) Physical Design Synthesis Floorplanning Placement Routing Equivalence Checking Timing Convergence ECO Deep Learning LLM
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Senior SOC/ASIC Physical Design Engineer

SpaceX

Irvine, CA +2 154 days ago $165,000–$260,000
Actively hiring Confirmed live today Low trust Competitive pay
ASIC Physical Design RTL2GDSII Static Timing Analysis STA FinFET CMOS DFT Scan MBIST LBIST Python TCL Perl Bash Makefile EDA Tools Floorplanning Place and Route Physical Verification Electromigration Voltage Drop
5+ yrs exp
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Senior SOC/ASIC Physical Design Engineer

SpaceX

Palo Alto, CA +3 154 days ago $175,000–$280,000
Actively hiring Confirmed live today Low trust Above market
ASIC Physical Design RTL2GDSII Static Timing Analysis STA FinFET CMOS DFT Scan MBIST LBIST Python TCL Perl Bash Makefile EDA Tools Floorplanning Place and Route Physical Verification Electromigration Voltage Drop
5+ yrs exp
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Senior SOC/ASIC Physical Design Engineer

SpaceX

Austin, TX +2 154 days ago
Actively hiring Confirmed live today Low trust
ASIC SOC Physical Design RTL2GDSII Static Timing Analysis STA Floorplanning Place and Route Physical Verification Electromigration Voltage Drop Logic Equivalency FinFET CMOS DFT Scan MBIST LBIST Python TCL Perl Bash Makefile EDA Tools
5+ yrs exp
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