Browse tech roles

ASIC Design RTL Design SoC Integration Logic Synthesis Timing Analysis Python Perl C++ UCIe Digital Design Verification Methodology Memory Controllers DMA Boot Controllers Fuse Controllers +10 more Show less

Python Claude Innovus ICC2 Calibre Tcl Docker OpenAI API Pinecone Weaviate RAG LLM MLPD STA DRC EDA Tools Vector Databases +12 more Show less

Verilog System Verilog ASIC Design RTL Timing Closure Clock Gating post silicon validation Scripting Micro-architecture +4 more Show less

ASIC UVM SystemVerilog Verilog Python Perl VCS Verdi Xcelium Automation RTL Pre-silicon Verification Scripting Infrastructure Simulation Debug Metrics +12 more Show less

STA Verilog SystemVerilog ASIC Design Physical Design Spice ECO Timing Analysis Extraction PnR +5 more Show less

SystemVerilog UVM Verilog Python Perl C C++ Linux ASIC Design Formal Verification Jasper Gold Veloce Palladium Zebu HAPS PCIe Ethernet RDMA TCP Fiber Channel P4 +16 more Show less

RTL ASIC FPGA Synthesis Static Timing Analysis Clock Domain Crossing CDC Bus Fabric Formal Verification Simulation JIRA FinFET TSMC GlobalFoundries Samsung EDA Tools Microarchitecture Power Analysis +13 more Show less

Verilog System Verilog ASIC Design RTL Python Perl TCL Micro-architecture Tape-out post silicon validation Simulation +6 more Show less

System Verilog UVM ASIC Design C C++ Python Perl Linux Formal Verification Networking Post-silicon Lab Bring-up +6 more Show less