ASIC Design Engineer Technical Lead

Cisco

Confirmed live today Low trust
Closes in 5 days

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$186,900–$267,700 / yr
Employment
Full-time
Posted
91 days ago
Freshness
Confirmed live today
Closes
Nov 1, 2026 (soon)
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $193k
This role $227k
$136k $282k
below market most similar roles pay here above market

This role pays more than 82% of similar roles. Most pay $168,200–$217,600 — the blue band above. At the midpoint, this role pays about $227k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer Technical Lead

Role Posting Log in to save

The ASIC Design Engineer Technical Lead joins the Common Hardware Group to develop innovative hardware platforms for switching, routing, and wireless products. This role involves contributing to chip architecture definition, authoring design specifications, and implementing Verilog RTL to meet specific timing and performance requirements. The engineer will mentor junior staff, collaborate with verification and physical design teams to close code coverage and timing issues, and perform diagnostic post-silicon validation tests. Key technical requirements include proficiency in Verilog and SystemVerilog, interactive waveform debugging, and experience delivering designs from specification to tape-out. Preferred skills include scripting in Python, Perl, TCL, or shell programming. The work focuses on solving complex hardware problems within the silicon and optics space to power core networking infrastructure.

Skills

ASIC Design Verilog System Verilog Python Perl TCL Shell Programming RTL Micro-architecture Tape-out post silicon validation Simulation

What you'll do

  • Contribute to chip architecture definition and micro-architecture specification reviews.
  • Author detailed design specifications for hardware components.
  • Implement Verilog RTL to meet specific timing and performance requirements.
  • Define, evolve, and support the internal design methodology.
  • Mentor junior engineers on project tasks and technical problem-solving.
  • Collaborate with verification and physical design teams to resolve bugs and timing issues.
  • Triage and root cause simulation, software bring-up, and customer failures.
  • Perform diagnostic and post-silicon validation tests in the lab.

What we're looking for

  • Bachelor’s degree in Electrical or Computer engineering with 8+ years of ASIC Design experience.
  • Master’s degree in Electrical Engineering or Computer Engineering with 6+ years of ASIC Design experience.
  • PhD in Electrical Engineering or Computer Engineering with 3 years of ASIC Design experience.
  • Verilog/System Verilog programming experience.
  • Interactive and waveform debug experience.
  • Experience delivering ASIC designs from specification to tape-out.
  • Experience in architecture and micro architecture development.
  • Experience resolving setup and hold timing violations with RTL modification (preferred).
  • Scripting experience in Python, Perl, TCL, or shell programming (preferred).
  • Demonstrated ability in troubleshooting and debugging (preferred).
  • Good written and verbal communication skills (preferred).

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