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11 of up to 20 (filtered)

ASIC Physical Design and Timing Engineer, New College Grad 2026

Nvidia

Santa Clara, CA 2 days ago $116,000$189,750
Actively hiring Posted this week Verified listing Below market
STA EDA tools Timing Constraints Synthesis Equivalence Checking Floor-planning Physical Design Deep Sub-micron Process Nodes AI/LLM Python C++ Perl Tcl Shell Scripting

Physical Design Engineer

Qualcomm

Santa Clara, CA 3 days ago $107,400$161,200
Actively hiring Posted this week Verified listing Below market
Verilog SystemC Python Perl C++ Linux Git SVN JIRA Confluence CI/CD Docker Kubernetes AWS Google Cloud Platform PostgreSQL Mentor Graphics Calibre Cadence Virtuoso Synopsys IC Compiler

Senior Staff CPU Physical Design CAD Engineer

Qualcomm

Santa Clara, CA +1 9 days ago $198,700$298,100
Actively hiring Above market
Tcl Python Cadence_Innovus Place-and-route Physical_Design Timing_Analysis Physical_Verification EDA Automation CI/CD

CPU Server Physical Design Clock Engineer

Qualcomm

Austin, TX +1 12 days ago $148,300$222,500
Actively hiring Competitive pay
SPICE Python Kubernetes Terraform Docker CI/CD Prometheus Grafana PostgreSQL Git VLSI RTL Physical_Design Clock_Tree_Synthesis HDL Verilog SystemVerilog Cadence Synopsys Calibre

Senior ASIC Physical Design Engineer, Netlisting

Nvidia

Santa Clara, CA +1 18 days ago $136,000$218,500
Actively hiring Competitive pay
Perl TCL Make Python RTL Logic Synthesis Static Timing Analysis Clock Domain Crossing Checking MTBF Analysis EDA Tools DFT Timing Closure Industry Standard EDA Tools Equivalence Checking/FV
Hybrid

Senior Software R&D Engineer, VLSI Physical Design

Nvidia

Santa Clara, CA +1 31 days ago $168,000$264,500
Actively hiring Above market
C++ C++17 C++14 computational_geometry placement routing graph_theory ICC2 Innovus algorithm_development GUI_development machine_learning CAD_software VLSI_design CI/CD
Hybrid

ASIC Physical Design Engineer, Netlisting

Nvidia

Santa Clara, CA +1 52 days ago $116,000$189,750
Actively hiring Below market
Perl TCL Make Python Synopsys Cadence Logic Synthesis Equivalence Checking Formal Verification Clock Domain Crossing Checks MTBF Analysis RTL Design EDA Tools AI Utilization

GPU Physical Design Engineer

Apple Inc

Santa Clara, CA 68 days ago $181,100$318,400
Actively hiring Above market
TCL Perl Python Synthesis DFT Floorplanning Clock_and_Power_Distribution Place_and_Route Timing_Electrical_Physical_Signoff Multi_Voltage_Design Power_Gating Hierarchical_Design Top_down_Design_Budgeting IP_Integration Design_for_Yield Thermal_Management CAD_Tools Floorplanning_Tools P&R_Flows Static_Timing_Analysis Physical_Design_Verification_Flows

CPU Physical Design Methodology and Optimization Engineer

Apple Inc

Santa Clara, CA 73 days ago $147,400$272,100
Actively hiring Above market
TCL Perl Python Synthesis PnR STA Physical_Design Digital_Circuits Timing Power_Concepts Logic_Design High_Performance_Physical_Design Low_Power_Physical_Design Deep_Sub_Micron_Technology

CPU Server Physical Design Engineer

Qualcomm

Santa Clara, CA 74 days ago $167,100$250,700
Actively hiring Above market
C C++ Python Perl Verilog VHDL UVM SystemC Cadence Synopsys ModelSim Tensilica Instruction Extension (TIE) Linux