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RF Analog IC Design Mixed-Signal Design RFIC Cadence HFSS MATLAB Perl Python Verilog SystemVerilog Tcl Shell RTL DFT SerDes PCIe USB DDR HBM SIPI PDN +17 more Show less

SystemVerilog Python MATLAB SPICE Perl Digital Logic Co-simulation Formal Equivalence Numerical Analysis Circuit Simulation +5 more Show less

C Assembly ARM Git Perforce Verilog RTL Mixed-Signal Post-Silicon Bringup System Integration Debugging +6 more Show less

SystemVerilog Python MATLAB SPICE Perl Digital Logic Co-simulation Formal Equivalence Numerical Analysis Circuit Simulation Verification +6 more Show less

SystemVerilog Verilog SPICE Python Perl Digital Logic Circuit Simulation Formal Equivalence Numerical Analysis SERDES +5 more Show less

RF Mixed‑Signal Python C# Lab Automation Spectrum Analyzers Oscilloscopes Logic Analyzers JTAG DSP Embedded Systems PCB Design Statistical Data Analysis AI‑assisted tools DFT Planning silicon bring‑up +11 more Show less

CMOS Mixed Signal Design Cadence ADE MATLAB SPICE Verilog VHDL PLL SERDES 5G Analog Design Automation Layout Silicon Evaluation +8 more Show less

ASIC Mixed-Signal Analog Front Ends (AFE low power design Sensor Fusion Edge AI Machine Learning CMOS Chiplets System-in-Package Firmware Embedded Systems Robotics IoT Functional Safety +10 more Show less

Cadence Virtuoso ASIC Design SerDes DDR PLL DAC ADC Python MATLAB SPICE Verilog VHDL Circuit Simulation Schematic Capture FinFET CMOS +11 more Show less

Mixed-Signal IC Design CMOS FinFET Cadence SPICE MATLAB Verilog VHDL ASIC Layout Data Converters PLL Analog Design Automation ATE Verification +10 more Show less

Cadence Virtuoso ASIC Design SerDes PLL DAC ADC Matlab Python SPICE Verilog VHDL CMOS FinFET Signal Processing Schematic Capture +10 more Show less

DDR SerDes Python Firmware ASIC Signal Integrity Oscilloscopes Spectrum Analyzers Logic Analyzers Machine Learning Data Science Statistical Modeling Soldering Regression Testing JEDEC +10 more Show less

System Verilog UVM Mixed-Signal Verification RF Verilog Python Matlab UPF Virtuoso Composer ADE HED HDL SOC +8 more Show less

System Verilog UVM Mixed-Signal Verification Verilog HDL Python Matlab UPF Virtuoso Composer ADE HED RF Analog Design Verification Methodology +9 more Show less