Mixed Signal SVE Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $140,000–$210,000 / yr
Posted: 12 days ago
Freshness: Confirmed live yesterday
Closes: Feb 26, 2027
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $179k

This role $175k

$131k most similar roles pay here $221k

This role pays more than 50% of similar roles. Most pay $146,450–$212,500 — the shaded band above. At the midpoint, this role pays about $175k versus about $179k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Mixed Signal SVE Engineer

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The Mixed Signal SVE Engineer joins the Mixed Signal SVE team to support silicon bring-up and validation of mixed signal IPs, specifically DDRPHY and SerDes. In this role, the engineer collaborates with cross-functional teams including PHY Design, Firmware, PTE, and Software to bring up PHYs and debug complex issues. Daily responsibilities include leading the debugging and optimization of DDR/SerDes PHYs across post-silicon teams, developing firmware, executing regression testing, and providing post-release support for customer issues. The role requires proficiency in Python scripting, knowledge of JEDEC specifications, and an understanding of PHY circuitry fundamentals like DLLs and calibration. Candidates must be skilled with lab instruments such as oscilloscopes and logic analyzers while applying signal integrity techniques. Additionally, the position involves using machine learning and data science to enhance hardware validation and silicon debug workflows.

Skills

DDR SerDes Python Firmware ASIC Signal Integrity Oscilloscopes Spectrum Analyzers Logic Analyzers Machine Learning Data Science Statistical Modeling Soldering Regression Testing JEDEC

What you'll do

Lead the bring-up, debugging, and optimization of DDR and SerDes PHYs across post-silicon teams.
Identify and resolve technical issues to ensure successful product launches.
Provide post-release support for customer issues related to PHY components.
Develop firmware and execute regression testing for mixed signal IPs.
Generate detailed test reports and documentation for internal and external stakeholders.
Perform hands-on lab work including soldering, system instrumentation, and using oscilloscopes or logic analyzers.
Utilize Python scripting and data science techniques to automate data collection and analysis.

What we're looking for

Bachelor's degree with 4+ years of experience, Master's with 3+ years, or PhD with 2+ years in ASIC design, verification, validation, or integration.
Experience in bring-up, debugging, and optimization of DDR and SerDes PHYs.
Proficiency in firmware development and scripting, preferably using Python.
Solid understanding of JEDEC and other electrical/protocol specifications.
Strong grasp of PHY circuitry fundamentals including DLLs, I/O, and calibration.
Familiarity with signal integrity, probing techniques for memory buses, and use of lab instruments like oscilloscopes and logic analyzers.
Experience with hands-on lab work, including soldering and system instrumentation.
Knowledge of machine learning or data science techniques applied to hardware validation or silicon debug.