Mixed-Signal Verification Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $175,000–$308,500 / yr
Posted: 143 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $199k

This role $242k

$125k most similar roles pay here $328k

This role pays more than 84% of similar roles. Most pay $168,500–$229,100 — the shaded band above. At the midpoint, this role pays about $242k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3587 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2768 roles with salary data.

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At a glance

TL;DR · Mixed-Signal Verification Engineer

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Mixed-Signal Verification Engineer will join the wireless silicon development team to focus on the verification of RF and mixed-signal blocks and their interfaces within a wireless SoC. The role involves reviewing specifications, extracting features, defining verification plans, and developing top and block level testbenches using a UVM framework. Key responsibilities include building monitors and checkers for RF components, debugging failures, managing bug tracking, analyzing coverage, and writing scripts to automate flows while incorporating novel ideas like AI into the methodology. The candidate must possess expertise in System Verilog, Verilog, and UVM, with additional experience in UPF, Python, Matlab, Virtuoso Composer, ADE, and HED. This position addresses critical technical challenges in ensuring silicon-correct functionality for wireless products through close collaboration with analog design and digital verification teams.

Skills

System Verilog UVM Mixed-Signal Verification Verilog HDL Python Matlab UPF Virtuoso Composer ADE HED RF Analog Design Verification Methodology

What you'll do

Review specifications and extract features to define and execute verification plans.
Develop top and block level Mixed Signal and Digital testbenches using the UVM framework.
Build and reuse monitors and checkers for RF and Mixed-Signal blocks.
Debug failures, fix testbench or model issues, and manage bug tracking.
Analyze and close coverage to ensure silicon-correct functionality.
Write scripts to automate verification flows.
Improve Mixed Signal verification methodologies by incorporating novel ideas and AI.

What we're looking for

Bachelor's degree and at least 10 years of relevant industry experience.
Experience with RF/Mixed-Signal blocks and SoCs.
Expertise in building Mixed-Signal testbenches, checkers, and tests using SystemVerilog.
Proficiency in UVM methodology and HDL (SystemVerilog, Verilog) for verification.
Strong problem-solving, testing, and debugging skills.
Understanding of common analog/RF blocks.
Experience with UPF, Python, or Matlab (preferred).
Experience with Virtuoso Composer, ADE, HED, wireless systems, or real-numbered analog behavioral models (preferred).

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