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System Verilog UVM Python Perl RTL SoC Verification Constrained Random Verification Functional Coverage Computer Architecture Digital Design Verification Methodology +6 more Show less

System Verilog Verilog Python C C++ RTL VLSI SoC UPF ATE Firmware Digital Design Analog Co-simulation Timing Simulation +9 more Show less

SystemVerilog Python Perl C C++ Tcl Shell Makefile RTL VLSI Design CMOS Formal Verification Functional Coverage Computer Architecture Linting Synthesis +11 more Show less

System Verilog Verilog UVM OVM VMM Python C++ Perl SVA RTL AMBA Waveform Analysis Digital Logic Design Chip Architecture Microarchitecture +10 more Show less

Verilog Python C++ C TCL Matlab Perl SoC IP Digital Design Micro-architecture Test-bench Regression Data Analysis Machine Learning +10 more Show less

Verilog C/C++ Python Unix Linux SoC PCIe DDR USB SPI I2C UART DMA Object-Oriented Programming Scripting Multi-processor Systems Digital Design Mixed-Signal Models +13 more Show less

System Verilog Verilog UVM Python Perl VCS Verdi Indago Digital Design Computer Architecture Constrained Randomization Assertion Methodology ASIC SoC Mixed Signal +10 more Show less

SystemVerilog C Python Perl Shell Scripting Verilog VCS Verdi MATLAB Digital Electronics CPU Architecture Regression Automation Functional Coverage RTL Design +9 more Show less

SystemVerilog UVM Python C/C++ Perl Digital Simulation Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Computer Architecture Digital Design PCI Express DisplayPort MIPI TCP/IP Ethernet NVLink Infiniband Assembly +15 more Show less

SystemVerilog UVM Python Perl C/C++ Assembly Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Digital Simulation Computer Architecture PCI Express DisplayPort MIPI Data Structures and Algorithms +11 more Show less

SystemVerilog UVM Python Perl C++ Assembly Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Digital Simulation Computer Architecture PCI Express DisplayPort MIPI Data Structures and Algorithms +11 more Show less

DFT Design Verification GPU SoC Python Perl TCL Gate Level Simulation Random Verification Coverage Analysis Assertions Logic Design Object-Oriented Programming Automation Scripts +9 more Show less

SystemVerilog Verilog Python Perl C++ C Assembly Digital Simulation Computer Architecture Debug +5 more Show less

DFT Design Verification Gate Level Simulation Python Perl TCL Object-Oriented Programming Coverage Analysis Assertions Pre-silicon Verification Logic Design GPU SoC Automation Scripts Regressions +10 more Show less

DFT Design Verification Gate Level Simulation Python Perl TCL Object-Oriented Programming Coverage Analysis Assertions Pre-silicon Verification Silicon Bring-up Logic Design Test Benches Random Verification Automation Scripts +10 more Show less

System-Verilog Verilog Verilog-AMS mixed signal verification RTL Python TCL Skill PERL Gate Level Simulation Assertions Waveform Viewers Coverage Collection Compute Clusters Analog Behavioral Models +10 more Show less

System Verilog UVM C C++ Python Perl EDA Tools Digital Design Computer Architecture Constrained Random Verification Functional Coverage ASIC Design Flow High-speed Interface Protocols Regression Analysis Verification IP +10 more Show less