Design Verification Engineer

What you'll do

• Review SoC, IP, and subsystem specifications to understand design requirements and functionality.
• Develop and maintain comprehensive test plans and coverage plans for hardware components.
• Write and execute simulation-based verification tests using System Verilog.
• Debug simulation failures by analyzing waveforms, error logs, and internal signals to identify root causes.
• Track verification progress and update test coverage metrics using internal project management tools.
• Document test methodologies, debugging procedures, and verification results for team knowledge.
• Develop Verification IP, reference models, and checkers using C and C++.
• Create automation tools and perform regression analysis using Python and Perl.

What we're looking for

• Bachelor’s degree or foreign equivalent in Electrical Engineering, Electronics Engineering, or a related field.
• 3 years of experience in the job offered or a related occupation.
• 3 years of experience using System Verilog for constrained random verification and functional coverage.
• 3 years of experience using UVM to develop verification environments and implement test cases.
• 3 years of experience using C and C++ to develop Verification IP, including reference models and checkers.
• 3 years of experience using Python and Perl for automation tools, constraint generation, and regression analysis.
• 3 years of experience using EDA tools for testbench simulations, debugging, and coverage closure.
• 3 years of experience using High-speed interface protocols for verifying high bandwidth, low power data communication systems.