Design Verification Engineer

Apple Inc

Confirmed live 2 days ago High trust

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $155,896–$225,300 / yr
Posted: 8 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $188k

This role $191k

$125k most similar roles pay here $236k

This role pays more than 60% of similar roles. Most pay $159,750–$216,250 — the shaded band above. At the midpoint, this role pays about $191k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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As a Design Verification Engineer, you will join the hardware team to review SoC, IP, and subsystem specifications to ensure design requirements and functionality are met. You will develop and maintain comprehensive test plans and coverage plans while writing and executing simulation-based verification tests for hardware components. Your daily work involves collaborating with design and micro-architecture teams to clarify features, debugging simulation failures by analyzing waveforms and error logs, and tracking progress using internal project management tools. The role requires proficiency in System Verilog for constrained random verification, UVM for developing verification environments, and C/C++ for creating Verification IP including reference models. You will also utilize Python and Perl for automation and regression analysis while applying knowledge of digital design, computer architecture, and high-speed interface protocols to verify complex data communication systems.

Skills

System Verilog UVM C C++ Python Perl EDA Tools Digital Design Computer Architecture ASIC High-speed Interface Protocols Simulation Regression Analysis Functional Coverage Constrained Random Verification

What you'll do

Review SoC, IP, and subsystem specifications to understand design requirements and functionality.
Develop and maintain comprehensive test plans and coverage plans for hardware components.
Write and execute simulation-based verification tests using System Verilog.
Debug simulation failures by analyzing waveforms, error logs, and internal signals to find root causes.
Track verification progress and update coverage metrics using internal project management tools.
Document test methodologies, debugging procedures, and verified results for team knowledge sharing.
Develop Verification IP including reference models and checkers using C and C++.
Create automation tools and perform regression analysis using Python and Perl.

What we're looking for

Bachelor's degree or foreign equivalent in Electrical Engineering, Electronics Engineering, or a related field.
3 years of experience in the role offered or a related occupation.
3 years of experience using System Verilog for constrained random verification and functional coverage.
3 years of experience using UVM to develop verification environments and implement test cases.
3 years of experience using C and C++ to develop Verification IP, including reference models and checkers.
3 years of experience using Python and Perl for automation tools, constraint generation, and regression analysis.
3 years of experience using EDA tools for testbench simulations, debugging, and coverage closure.
Experience with high-speed interface protocols, Digital Design, and Computer Architecture.

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