Design Verification Engineer

What you'll do

• Review design requirements and develop architectural specifications with architecture and design teams.
• Develop SystemVerilog golden reference models to mimic the logical behaviors of RTL designs.
• Create SystemVerilog assertions and checkers for testing RTL designs.
• Develop directed tests and constrained random stimulus using Assembly, Perl, or Python.
• Run test simulations on RTL designs using simulator and emulator tools.
• Debug failures in RTL simulations and collaborate with the design team to fix bugs.
• Develop coverage constructs and analyze functional coverage from RTL regressions.
• Perform formal verification of designs using Jasper formal tool and develop automated checks.

What we're looking for

• Master's degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field.
• Knowledge of basic semiconductor physics, CMOS/VLSI design, and computer and processor architecture.
• Experience in design verification and functional coverage.
• Ability to develop RTL for digital logic blocks using SystemVerilog, including linting and synthesis readiness.
• Knowledge of low-power techniques such as clock gating, power gating, and multi-voltage designs.
• Experience in computer architecture specification and performance analysis.
• Proficiency in object-oriented programming, C, C++, SystemVerilog, Python, Perl, and algorithms.
• Proficiency in testing and scripting using Perl, Tcl, shell, Makefile, and Python.