PMU Design Verification Engineer: Analog & Mixed Signal Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $150,400–$277,600 / yr
Posted: 17 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $205k

This role $214k

$132k most similar roles pay here $293k

This role pays more than 65% of similar roles. Most pay $168,500–$240,550 — the shaded band above. At the midpoint, this role pays about $214k versus about $205k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3587 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2768 roles with salary data.

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At a glance

TL;DR · PMU Design Verification Engineer: Analog & Mixed Signal Engineer

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PMU Design Verification Engineer: Analog & Mixed Signal Engineer will join the analog and mixed signal verification team to ensure high-quality silicon for IC chips and IPs. This role involves full-chip verification of state-of-the-art mixed-signal systems, where you will perform pre-silicon verification by combining analog circuits and RTL in shared simulations. Daily responsibilities include reviewing specifications, developing detailed test and coverage plans, building scalable verification environments with assertions and trackers, triaging issues, and managing the process from initial architectural discussions through tape-out. You will utilize hardware descriptive languages like Verilog, SystemVerilog, and Verilog-AMS, alongside scripting in TCL, Skill, Python, or PERL. The role focuses on power management and auxiliary circuitry, including switching converters, linear converters, reference circuitry, bandgaps, data converters, and clock generators to solve complex mixed-signal design challenges.

Skills

mixed signal verification Verilog System-Verilog Verilog-AMS RTL Assertion Check Gate Level Simulation TCL Skill Python Perl Coverage Collection Simulation Waveform Viewers Power Management

What you'll do

Develop detailed test and coverage plans based on specific IC requirements.
Build verification environments including stimuli, checkers, assertions, and trackers.
Verify mixed-signal designs using a combination of analog circuits and RTL in shared simulations.
Execute full pre-silicon verification cycles from initial architecture discussions to tape-out.
Create scalable and portable verification methodologies for various IPs.
Identify failure mechanisms and triage issues during the simulation process.
Run and optimize simulations across compute clusters to manage wall time.
Sign off on mixed-signal designs to ensure production-quality first silicon.

What we're looking for

Bachelor of Science degree and at least 3 years of relevant industry experience.
Ability to verify analog/mixed-signal designs in a collaborative team environment (preferred).
Proficiency in hardware descriptive languages such as Verilog, SystemVerilog, and/or Verilog-AMS (preferred).
Familiarity with authoring analog assertion checks to catch bugs (preferred).
Capability to identify failure mechanisms and review verification results in analog IC designs (preferred).
Ability to write test plans, present results, and communicate clearly with multi-functional teams (preferred).
Comfort running simulations through compute clusters while optimizing simulation and wall time (preferred).
Understanding of power management and auxiliary circuitry like converters, reference circuitry, and clock generators (preferred).

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