This role pays more than
50%
of similar roles. Most pay
$168,500–$229,100
— the shaded band above.
At the midpoint, this role pays about
$188k
versus about
$199k
for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
3553 open roles
on FindRole.
Listed pay typically runs
$165,800–$277,600
across 2740 roles with salary data.
As a Design Verification Engineer, you will join the hardware team to ensure the integrity of complex designs through rigorous verification processes. Your daily responsibilities include reviewing design specifications and test plans with cross-functional teams, generating coverage databases, and developing regression scripts on internal infrastructure. You will build reusable, scalable testbenches featuring directed and constrained random tests while developing functional coverage metrics and checkers to identify bugs. To succeed, you must utilize SystemVerilog for test development, C for reference models, and Perl, Python, or shell scripting for automation. The role requires expertise in Digital Electronics, Verilog RTL design constructs, and CPU architecture knowledge to verify CPU-based designs. You will also use MATLAB for modeling and tools like VCS or Verdi for simulation and waveform debugging to resolve identified RTL issues.
What does a Design Verification Engineer earn in California?
Median $189224 from 46 postings across 7 companies.
System Verilog
UVM
C
C++
Python
Perl
EDA Tools
Digital Design
Computer Architecture
ASIC
High-speed Interface Protocols
Simulation
Regression Analysis
Functional Coverage
Constrained Random Verification
UVM
System Verilog
Python
C++
System C
SVA
Coverage Driven Verification
LLM
Prompt Engineering
RTL Simulation
4G/5G
3GPP
AXI
AHB
NoC
Bus Fabric
Perl
Automation