Design Verification Engineer

What you'll do

• Ensure the quality of SOCs, IPs, or subsystems through rigorous verification processes.
• Review design and architecture specifications to understand functional and performance goals.
• Develop comprehensive test plans, coverage plans, and next-generation verification methodologies.
• Build scalable and reusable testbenches for SoC verification using SystemVerilog and UVM.
• Create constrained random stimulus for RTL design-under-test (DUT) verification.
• Automate testbench simulation flows using Perl and Python scripting.
• Run and triage regressions while tracking bugs to achieve high coverage results.
• Analyze functional coverage metrics to ensure complete verification of SoC designs.

What we're looking for

• Master's degree or foreign equivalent in Electrical and Computer Engineering, Electronics Engineering, or a related field.
• Experience using SystemVerilog to build scalable and reusable testbenches for SoC verification.
• Proficiency in Perl and Python scripting for automating testbench simulation flows.
• Knowledge of digital design concepts for functional verification of RTL DUT.
• Application of Computer Architecture concepts to verify SoC architecture and design.
• Ability to use SystemVerilog to create constrained random stimulus for RTL DUT verification.
• Experience using UVM to build testbenches for constrained random verification of SoC IPs.
• Knowledge of design verification concepts such as functional coverage metrics for SoC design verification.