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Active Keyword: CPU Micro Remove filter Location: Austin Remove filter Clear all

6 of up to 20 (filtered)

CPU Micro-Architect RTL Engineer

Qualcomm

Austin, TX 3 days ago $98,500–$147,700
Actively hiring Posted this week Verified listing Below market
RISC-V RTL CPU microarchitecture Processor pipelines Out-of-order execution Load/store units Caches Cache coherence Memory hierarchy Multi-processor systems Multi-threaded systems Low-power optimizations Performance exploration Area and timing goals
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CPU RTL/AI Micro-Architect - AI Development

Qualcomm

Austin, TX 18 days ago $179,000–$268,400
Actively hiring Above market
AI Python Verilog SystemVerilog VHDL Kubernetes Docker CI/CD Prometheus Grafana AWS Git Jenkins PostgreSQL SQLite
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CPU Micro-Architecture and RTL Design Engineer (RISC-V)

Qualcomm

Santa Clara, CA +1 42 days ago $167,100–$250,700
Actively hiring Competitive pay
Verilog VHDL Perl Python RTL Microarchitecture Instruction_fetch_and_decode Branch_prediction Out_of_order_execution Integer_and_floating_point_execution Load_store_execution Prefetching Cache_and_memory_subsystems Logic_design_principles Timing_and_power_implications Low_power_microarchitecture_techniques
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CPU Micro-Architect RTL Engineer

Qualcomm

Austin, TX 42 days ago $154,000–$231,000
Actively hiring Competitive pay
RISC-V RTL Verilog SystemC VHDL Processor pipelines Out-of-order execution Load/store units Caches Cache coherence Memory hierarchy Multi-processor systems Multi-threaded systems Low-power design Performance optimization Area and timing goals Communication skills Collaboration skills Teamwork skills
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CPU Performance – Principal Microarchitecture Exploration Engineer

Arm Holdings

Austin, TX +1 60 days ago $249,900–$338,100
Actively hiring Above market
C++ Python Cycle-accurate simulators Performance modeling infrastructure High-performance CPU microarchitecture Performance profiling CI/CD Kubernetes AWS Git JIRA Confluence GitHub Docker Prometheus Grafana
Hybrid
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CPU Micro-architect/RTL Designer (Multiple Locations)

Qualcomm

Austin, TX +1 94 days ago $148,300–$250,700
Actively hiring Competitive pay
Verilog VHDL Perl Python Waveform debugging tools Simulators Instruction fetch and decode Branch prediction Instruction scheduling Register renaming Out-of-order execution Integer execution Floating point execution Load/store execution Prefetching Cache subsystems Memory subsystems Logic design principles Timing analysis Power analysis Low power techniques High performance techniques
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