Browse tech roles

Basic role filtering by workplace, salary floor, and post age. For full AI matching and advanced filtering upload your resume using AI Match.

Active Keyword: CPU Micro Remove filter Location: Austin Remove filter Clear all

14 of up to 20 (filtered)

CPU Performance, Principal Microarchitecture Exploration Engineer

Arm Holdings

Austin, TX +1 8 days ago $249,900–$338,100
Actively hiring Confirmed live yesterday High trust Above market
CPU Microarchitecture Performance Modeling Cycle-accurate Simulators C++ Python Workload Analysis Performance Profiling power, and area trade-offs Software Engineering Practices
10+ yrs exp Hybrid
Save

CPU Micro-Architecture and RTL Design Engineer (RISC-V)

Qualcomm

Santa Clara, CA +1 25 days ago $175,600–$263,400
Actively hiring Confirmed live today Trusted Competitive pay
RISC-V RTL Design Verilog VHDL Microarchitecture Python Perl Logic Design Functional Verification Waveform Debugging Simulators Out-of-Order Execution
4+ yrs exp
Save

Principal Competitive CPU Microarchitecture & Platform Performance Engineer

Amd

Austin, TX 39 days ago $200,000–$300,000
Actively hiring Confirmed live yesterday High trust Above market
CPU Microarchitecture Performance Modeling System Architecture Hardware Performance Counters NUMA TLB PCIe CXL HBM DDR data-analysis Scripting Virtualization HPC Power Modeling ISA Telemetry Bottleneck Analysis
Save

CPU Micro-architect/RTL Designer

Qualcomm

Austin, TX +1 39 days ago $216,600–$325,000
Actively hiring Confirmed live today Low trust Above market
RTL Design Microarchitecture Verilog VHDL Python Perl Logic Design Functional Verification Waveform Debugging Simulators Out-of-Order Execution
8+ yrs exp
Save

CPU RTL/AI Micro-Architect

Qualcomm

Austin, TX +1 39 days ago $186,700–$280,100
Actively hiring Confirmed live yesterday High trust Competitive pay
Verilog SystemVerilog VHDL RTL Design LLM Agentic AI Simulation Waveform Debug Logic Design Synthesis CPU Architecture Microarchitecture Hardware Engineering
6+ yrs exp
Save

CPU Microarchitect/RTL Engineer

Apple Inc

Austin, TX 40 days ago
Actively hiring Confirmed live yesterday Low trust
RTL Verilog VHDL Microarchitecture Logic Design Python Perl Verdi Simulation Waveform Debugging Instruction Fetch and Decode Branch Prediction Out-of-Order Execution Cache and Memory Subsystems Power and Area Tradeoffs
3+ yrs exp
Save

CPU Microarchitect/RTL Engineer

Apple Inc

Austin, TX 40 days ago
Actively hiring Confirmed live yesterday Low trust
RTL Verilog VHDL Microarchitecture Logic Design Python Perl Verdi Simulators Waveform Debugging Instruction Fetch and Decode Branch Prediction Out-of-Order Execution Cache and Memory Subsystems
10+ yrs exp
Save

CPU Microarchitect/RTL Engineer

Apple Inc

Austin, TX 40 days ago
Actively hiring Confirmed live today Low trust
RTL Verilog VHDL Microarchitecture Logic Design Python Perl Verdi Simulation Waveform Debugging CPU Architecture
Save

CPU Microarchitect/RTL Engineer

Apple Inc

Austin, TX 40 days ago
Actively hiring Confirmed live today Low trust
RTL Verilog VHDL Microarchitecture Python Perl Verdi Logic Design Simulators Waveform Debugging CPU Architecture Performance Verification
Save

CPU Microarchitect/RTL Engineer

Apple Inc

Austin, TX 40 days ago
Actively hiring Confirmed live yesterday Low trust
RTL Verilog VHDL Microarchitecture Logic Design Python Perl Verdi Simulators Waveform Debugging Instruction Fetch and Decode Branch Prediction Register Renaming Out-of-Order Execution Cache and Memory Subsystems
10+ yrs exp
Save

CPU Microarchitect/RTL Engineer

Apple Inc

Austin, TX 40 days ago
Actively hiring Confirmed live today Low trust
RTL Verilog VHDL Microarchitecture Python Perl Logic Design Simulators Verdi Instruction Fetch and Decode Branch Prediction Out-of-Order Execution Cache and Memory Subsystems Power and Area Tradeoffs
3+ yrs exp
Save

CPU Micro-architect/RTL Designer

Qualcomm

Austin, TX +1 40 days ago $175,600–$263,400
Actively hiring Confirmed live today Trusted Competitive pay
RTL Design Microarchitecture Verilog VHDL Python Perl Logic Design Functional Verification Waveform Debugging Out-of-Order Execution Simulators
Save

CPU Microarchitect/RTL Engineer

Apple Inc

Austin, TX 61 days ago
Actively hiring Confirmed live today Low trust
RTL Verilog VHDL Microarchitecture Logic Design Python Perl Verdi Simulation Waveform Debugging Instruction Fetch and Decode Branch Prediction Out-of-Order Execution Cache and Memory Subsystems
10+ yrs exp
Save

CPU Micro-architect

Samsung Electronics

San Jose, CA +1 67 days ago $124,000–$208,400
Actively hiring Confirmed live today Trusted Below market
CPU Microarchitecture C++ Python Verilog Arm ISA x86 RISC-V OoO CPU TLB Branch Prediction SpecInt17 GB6 Hardware Description Languages Root Cause Analysis
4+ yrs exp
Save