CPU Micro-architect/RTL Designer

Qualcomm

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
Austin, TXSanta Clara, CA
Salary
$148,300–$250,700 / yr
Posted
12 days ago
Freshness
Confirmed live yesterday
Closes
Feb 26, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $209k
This role $200k
$136k most similar roles pay here $263k

This role pays less than 52% of similar roles. Most pay $175,000–$243,562 — the shaded band above. At the midpoint, this role pays about $200k versus about $209k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · CPU Micro-architect/RTL Designer

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As a CPU Micro-architect/RTL Designer within the CPU Engineering group, you will contribute to the development of RTL for high performance, low power devices. You will collaborate with chip architects to conceive micro-architecture, perform performance exploration alongside the modeling team, and move from early architectural research to detailed specifications. Your daily responsibilities include RTL ownership, where you will develop, assess, and refine designs to meet specific power, performance, area, and timing goals while supporting functional and performance verification efforts. The role requires expertise in microprocessor architecture—including branch prediction, out-of-order execution, and memory subsystems—alongside proficiency in Verilog or VHDL, logic design principles, and scripting languages like Perl or Python. You will solve complex technical challenges involving low power microarchitecture techniques and high performance trade-offs for advanced processor designs.

Skills

RTL Verilog VHDL Python Perl Microarchitecture Logic Design Functional Verification Waveform Debugging Instruction Fetch Branch Prediction

What you'll do

  • Explore high performance strategies in collaboration with the CPU modeling team.
  • Develop microarchitecture specifications from early architectural exploration through detailed research.
  • Own RTL design by developing and refining code to meet power, performance, area, and timing goals.
  • Support the design verification team in executing functional verification strategies.
  • Verify that the RTL design meets established performance targets.
  • Collaborate with multi-functional teams to implement and validate physical design aspects like reliability and testability.

What we're looking for

  • Thorough knowledge of microprocessor architecture including fetch/decode, branch prediction, scheduling, and memory subsystems.
  • Knowledge of Verilog and/or VHDL.
  • Experience with simulators and waveform debugging tools.
  • Knowledge of logic design principles regarding timing and power implications.
  • Understanding of low power microarchitecture techniques.
  • Understanding of high performance techniques and trade-offs in CPU microarchitecture.
  • Experience using scripting languages such as Perl or Python.

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