CPU Micro-architect/RTL Designer

Qualcomm

Confirmed live today Trusted

Quick summary

Work type
On-site
Location
Austin, TXSanta Clara, CA
Salary
$175,600–$263,400 / yr
Posted
40 days ago
Freshness
Confirmed live today
Closes
Mar 16, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $216k
This role $220k
$153k $291k
below market most similar roles pay here above market

This role pays more than 52% of similar roles. Most pay $177,300–$254,750 — the blue band above. At the midpoint, this role pays about $220k versus about $216k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · CPU Micro-architect/RTL Designer

As a CPU Micro-architect/RTL Designer within the CPU Engineering group, you will develop RTL for high performance, low power devices. You will collaborate with chip architects to conceive micro-architectures, participate in early product life-cycle definitions, and perform performance exploration with the CPU modeling team. Your daily responsibilities include microarchitecture development, specification, and RTL ownership to meet power, performance, area, and timing goals. You will also provide functional and performance verification support and work with multi-functional teams on physical design implementation. Required skills include knowledge of microprocessor architecture, including branch prediction, out-of-order execution, and cache subsystems. You must possess proficiency in Verilog or VHDL, logic design principles, low power techniques, and scripting languages like Perl or Python to solve complex CPU design challenges.

What you'll do

  • Explore high-performance strategies in coordination with the CPU modeling team.
  • Develop and specify microarchitecture from high-level exploration to detailed specifications.
  • Develop, assess, and refine RTL design to meet power, performance, area, and timing goals.
  • Support the design verification team in executing the functional verification strategy.
  • Verify that the RTL design meets established performance goals.
  • Implement and validate physical design aspects including timing, area, reliability, and testability.

What we're looking for

  • Develop and refine RTL design to meet power, performance, area, and timing goals.
  • Perform microarchitecture development and specification from high-level exploration to detailed design.
  • Support functional and performance verification strategies for RTL designs.
  • Collaborate with multi-functional teams to implement and validate physical design aspects.
  • Thorough knowledge of microprocessor architecture including instruction fetch, branch prediction, and cache subsystems (preferred).
  • Knowledge of Verilog and/or VHDL and experience with simulators and waveform debugging tools (preferred).
  • Knowledge of logic design principles along with timing and power implications (preferred).
  • Understanding of low power and high performance techniques in CPU microarchitecture (preferred).

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