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15 of up to 20 (filtered)

Senior VLSI CAD Software Engineer

Nvidia

Santa Clara, CA +4 7 days ago $168,000$264,500
Actively hiring Confirmed live yesterday Posted this week High trust Above market
C++ Java C# VLSI CAD EDA C++20 Java 21 Git Visual Studio CLion CI/CD Object-Oriented Design Algorithms Data Structures AI-assistants
10+ yrs exp

CPU STA CAD Engineer

Qualcomm

Santa Clara, CA +1 11 days ago $198,700$298,100
Actively hiring Confirmed live yesterday High trust Above market
Static Timing Analysis Python Tcl CI/CD Synthesis PnR PPA Optimization Test Driven Development Scripting
6+ yrs exp

Senior CAD Automation and Mixed-Signal Simulation Engineer

Apple Inc

Austin, TX 14 days ago
Actively hiring Confirmed live yesterday High trust
AMS Python Perl C/C++ TCL Cadence Synopsys Siemens Spectre HSPICE Finesim SystemVerilog VerilogA Verilog Verilog-AMS VHDL Virtuoso SKILL ADE SPICE AI Agents
10+ yrs exp

Staff Engineer, Static Timing Analysis CAD Engineer

Samsung Electronics

Remote (Austin, TX) 15 days ago $151,000$226,600
Actively hiring Confirmed live yesterday High trust Competitive pay
Static Timing Analysis PrimeTime StarRC PrimeClosure Tempus Tcl Python Perl ASIC Design Flow Clock Tree Synthesis UPF POCV Multi-Corner Analysis Formal Equivalency Check
6+ yrs exp Remote

Senior Staff Engineer, Physical Implementation CAD Lead

Samsung Electronics

Remote (Austin, TX) 43 days ago $180,200$297,200
Actively hiring Confirmed live 2 days ago Trusted Above market
Physical Design CAD Python Tcl Shell Synthesis place-and-route Static Timing Analysis Power Optimization Cadence Synopsys Calibre ICV DTCO PPA SoC GPU
10+ yrs exp Remote

CPU Synthesis CAD Engineer

Qualcomm

Santa Clara, CA +2 43 days ago $198,700$298,100
Actively hiring Confirmed live 2 days ago High trust Above market
Synthesis Place-and-Route Tcl Python Cadence Genus Synopsys Fusion Compiler Logic Design Physical Design LEC UPF Front-end Signoff Automation Computer Architecture Micro-architecture
6+ yrs exp

CPU Integration CAD Engineer

Qualcomm

Santa Clara, CA +1 43 days ago $167,100$250,700
Actively hiring Confirmed live yesterday High trust Competitive pay
Python Tcl Innovus Calibre Floorplanning Power Planning Pin Placement DRC LVS place-and-route Timing Sign-off Automation Physical Design
4+ yrs exp

Senior Staff CPU Physical Design CAD Engineer

Qualcomm

Santa Clara, CA +2 43 days ago $198,700$298,100
Actively hiring Confirmed live 2 days ago High trust Above market
Physical Design Cadence Innovus Tcl Python Place-and-Route Timing Analysis Physical Verification Digital Design Automation Micro-architecture Logic Design
6+ yrs exp

IC CAD Engineer

Amd

San Jose, CA +1 74 days ago $141,760$212,640
Actively hiring Confirmed live yesterday High trust Competitive pay
Cadence Virtuoso LEF Calibre SKILL Perl PDK AI Agents Claude Code Schematic Layout CAD Flow Custom Design Verification
Hybrid

CAD Engineer, Signoff Infrastructure

Apple Inc

Austin, TX 137 days ago
Actively hiring Confirmed live yesterday Trusted
Python JavaScript TypeScript Angular React Express.js SQL Relational Databases CI/CD Linux Unix Full-stack Development RAG AI ML Version Control Web Development

CAD Engineer, Signoff Infrastructure

Apple Inc

Austin, TX 137 days ago
Actively hiring Confirmed live 2 days ago Trusted
Python JavaScript TypeScript Angular React Express.js SQL MySQL PostgreSQL CI/CD RAG LLM Vector Databases Kubernetes Prometheus Grafana Test-Driven Development
3+ yrs exp

Gate-level IR/EM CAD/NLP Engineer

Apple Inc

Austin, TX 142 days ago
Actively hiring Confirmed live 2 days ago Trusted
Machine Learning Large Language Models NLP Python CAD Flow TFM UNIX Shell IR/EM Analysis STA Timing Power Grid Extraction Data Structures Algorithms Retrieval Augmented Generation Prompt Engineering Dashboards
3+ yrs exp

Gate-level IR/EM CAD/NLP Engineer

Apple Inc

Austin, TX 142 days ago
Actively hiring Confirmed live yesterday Trusted
Machine Learning Large Language Models NLP Python CAD Flow IR/EM Analysis STA Timing UNIX Shell Data Structures Algorithms Retrieval Augmented Generation Prompt Engineering Code Revision Control Circuit-design Physical Design Power Grid Extraction
10+ yrs exp

CAD Engineer - Design Verification Methodology

Apple Inc

Austin, TX 148 days ago
Actively hiring Confirmed live 2 days ago Low trust
Python TCL Perl Verilog SystemVerilog VHDL Synopsys VCS Xcelium Modelsim Verdi Indago C C++ Makefile RTL Machine Learning Artificial Intelligence
3+ yrs exp

CAD Engineer - Design Verification Methodology

Apple Inc

Austin, TX 149 days ago
Actively hiring Confirmed live yesterday Low trust
Python TCL Perl Verilog SystemVerilog VHDL VCS Xcelium Modelsim Cadence Synopsys Verdi Indago C C++ Machine Learning RTL
10+ yrs exp