CAD Engineer, EMIR Signoff

Apple Inc

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Work type: On-site
Location: Austin, TX
Posted: 21 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Similar $209k

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

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TL;DR · CAD Engineer, EMIR Signoff

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As a CAD Engineer – EMIR Signoff within the Silicon Technologies group, you will join the advanced Signoff CAD team to ensure verification and analysis for complex mixed-signal designs prior to tapeout. You will develop, define, and refine signoff methodologies at both the gate and transistor levels, focusing on power/EMIR analysis. Daily responsibilities include performing functional static/dynamic IR analysis, scan-mode IVD analysis, package model handling, power EM analysis, signal EM, power switch modeling, and IP reuse. You will utilize industry-leading tools like Redhawk, Voltus, and Totem while applying Perl and Python scripting. The role involves defining signoff requirements, partnering with Design, CAD, and Technology teams to confirm EDA flows, and exploring AI/ML and LLM-driven techniques to accelerate analysis and automate flow debugging.

Skills

EMIR Analysis Redhawk Voltus Totem Python Perl Mixed-Signal Design CMOS EDA Flows Power Analysis Dynamic IR Analysis AI/ML LLM Scan-mode IVD Signoff Methodologies

What you'll do

Perform verification and analysis on complex mixed-signal designs prior to tapeout.
Develop and refine signoff methodologies for power/EMIR analysis at gate and transistor levels.
Execute functional static/dynamic IR analysis and scan-mode IVD analysis.
Manage package model handling, power EM analysis, and signal EM analysis.
Define signoff requirements early in the project lifecycle and confirm EDA flow setups.
Provide frontline support to design groups for enablement, enhancement, and debug requests.
Implement AI/ML and LLM-driven techniques to automate flow debugging and surface anomalies.

What we're looking for

Bachelor of Science degree.
Minimum of 3 years of relevant industry experience.
Experience in CAD, EMIR analysis, or related circuit design roles.
Solid understanding of circuit design principles and EMIR analysis at the transistor and gate level across multiple modes (preferred).
In-depth knowledge of industry-leading tools such as Redhawk, Voltus, and Totem (preferred).
Experience in simulation and power analysis to verify circuit performance (preferred).
Strong understanding of CAD flows (preferred).
Proficiency in scripting/programming languages such as Perl and Python (preferred).

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