3D IC and SoC CAD Engineer

Amd

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$144,800–$217,200 / yr
Posted
27 days ago
Freshness
Confirmed live yesterday
Closes
Sep 30, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $210k
This role $181k
$130k $279k
below market most similar roles pay here above market

This role pays less than 70% of similar roles. Most pay $177,250–$243,600 — the blue band above. At the midpoint, this role pays about $181k versus about $210k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · 3D IC and SoC CAD Engineer

The 3D IC and SoC CAD ENGINEER joins a global CAD team to deliver automated environments for 3D IC stack and advanced packaging design. This role involves implementing and maintaining design flows from RTL through signoff, leading hands-on debug for large chip-level physical and logical netlists, and partnering with EDA vendors on feature requirements. The engineer will develop and integrate end-to-end AI capabilities, including ML-based optimization and LLM-assisted automation, to improve quality of results. Key technical requirements include proficiency in Python, TCL, and Perl within Linux environments, alongside experience with tools like ICC2, Innovus, and Primetime. The role addresses the increasing complexity of heterogeneous systems, specifically focusing on 3D, 2.5D, and 3.5D packaging technologies, including interposers, silicon bridges, and advanced-node tapeouts.

What you'll do

  • Implement and maintain 3D-IC and advanced packaging design flows from RTL through signoff.
  • Lead hands-on debug and automation for large chip-level physical and logical netlists.
  • Partner with EDA vendors to define 3D-IC feature requirements and AI co-development opportunities.
  • Develop and integrate ML-based optimization, predictive modeling, and LLM-assisted automation into CAD flows.
  • Define strategies and initiatives to ensure flows meet requirements for future technology nodes.
  • Regress methodology and analyze results to develop capabilities that improve quality of results.
  • Deliver tools and flows to design teams that meet key Timing, Area, and Performance metrics.

What we're looking for

  • Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.
  • Strong silicon hardware design background.
  • Scripting proficiency in Python, TCL, and Perl within a Linux/Unix environment.
  • Hands-on experience applying machine learning to CAD or EDA workflows.
  • Strong understanding of industry EDA tools, specifically place-and-route, extraction, and analysis tools (preferred).
  • Familiarity with chip- or system-level netlists and ability to debug connectivity across industry-standard formats (preferred).
  • Exposure with system-level design verification processes including LEC, LVS, and DRC (preferred).
  • Experience with advanced-node tapeouts across silicon technologies (preferred).

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