CAD Engineer, EMIR Signoff

What you'll do

• Perform verification and analysis on complex mixed-signal designs prior to tapeout.
• Develop and refine signoff methodologies for power/EMIR analysis at the gate and transistor levels.
• Execute functional static/dynamic IR analysis and scan-mode IVD analysis.
• Manage package model handling, power EM analysis, signal EM, and power switch modeling.
• Define signoff requirements early in the project lifecycle and confirm EDA flow setups.
• Provide frontline support to design groups for enablement, enhancement, and debug requests.
• Implement AI/ML and LLM-driven techniques to automate flow debugging and surface design anomalies.

What we're looking for

• Bachelor of Science degree.
• Minimum of 10 years of relevant industry experience.
• Experience in CAD, EMIR analysis, or related circuit design roles (preferred).
• Solid understanding of circuit design principles and EMIR analysis at the transistor and gate level (preferred).
• In-depth knowledge of industry-leading tools such as Redhawk, Voltus, and Totem (preferred).
• Experience in simulation and power analysis to verify circuit performance (preferred).
• Strong understanding of CAD flows (preferred).
• Proficiency in scripting/programming languages such as Perl and Python (preferred).