Gate-level SigEM/SEB/FIT CAD Engineer

What you'll do

• Develop, test, and deploy EM, SEB, and thermal analysis methodologies and flows.
• Automate, maintain, and perform regression testing on CAD flows from setup through sign-off.
• Run, validate, and debug simulation and verification runs on benchmark and production designs.
• Develop and maintain verification scripts and rule checks for clock trees and high-speed data paths.
• Perform signal EM analysis for clock and data nets and SOC FIT budget verification.
• Execute power-grid EM checks and thermal analysis for gate-level and transistor-level designs.
• Triage flow execution issues and gather data for cross-functional physical design and timing teams.

What we're looking for

• BS or MS degree in Electrical Engineering or a related field.
• Strong academic foundation in VLSI design, semiconductor physics, circuit theory, or computer engineering (preferred).
• Basic understanding of electromigration (EM) mechanisms, heating effects, current density, or chip reliability concepts (preferred).
• Exposure to concepts in static timing analysis (STA), circuit simulation (SPICE), parasitic extraction, or physical design principles (preferred).
• Proficiency in at least one of Tcl, Python, or Perl scripting languages (preferred).
• Prior internship, co-op, or academic research experience in VLSI design, CAD/EDA flow development, or chip reliability (preferred).
• Familiarity with commercial EDA tools like Voltus, RedHawk, Primetime, ICC2, Innovus, or SPICE simulators (preferred).
• Curiosity about or coursework in AI/ML applications in CAD/EDA workflows (preferred).