Staff Engineer, Memory Systems Architecture

Samsung Semiconductor

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$163,000–$253,000 / yr
Posted
175 days ago
Freshness
Confirmed live 2 days ago

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $207k
This role $208k
$152k most similar roles pay here $264k

This role pays more than 51% of similar roles. Most pay $177,250–$236,128 — the shaded band above. At the midpoint, this role pays about $208k versus about $207k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

Samsung Semiconductor currently has 49 open roles on FindRole.

Listed pay typically runs $163,000–$253,000 across 49 roles with salary data.

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At a glance

TL;DR · Staff Engineer, Memory Systems Architecture

Staff Engineer, Memory Systems Architecture joins an incubation team focused on in-field telemetry to improve the customer quality experience for memory products. This role involves analyzing large volumes of memory fleet telemetry to identify failure modes and perform virtual root-cause analysis to minimize system downtime in AI/ML hardware environments. You will develop platform RAS algorithms such as page offlining, hPPR, and hardware sparing while contributing to the standardization of DRAM and HBM failure logging in the OCP. Key responsibilities include recommending solutions to mitigate field DRAM failure rates, communicating ECC schemes to customers, and performing proof of concepts with known failure DIMMs. Required expertise includes SOC controller knowledge, memory subsystem understanding, Linux kernel commit experience, and proficiency in ECC design, verification, and reverse engineering for both DRAM and HBM technologies.

What does a Engineer earn in California?

Median $208000 from 94 postings across 22 companies.

See salary data

What you'll do

  • Analyze large datasets of memory fleet telemetry to identify failure modes and project failure rates.
  • Develop solutions to proactively mitigate field DRAM failures based on SOC controller and memory operation knowledge.
  • Communicate advanced ECC schemes to customers based on specific DRAM failure modes like DQ and burst.
  • Interface with customers to demonstrate the value of in-field fault management architectures.
  • Contribute to the standardization of DRAM and HBM failure logging within the OCP.
  • Develop platform RAS algorithms such as page offlining and hPPR for memory fault management.
  • Conduct proof-of-concept testing with known failure DIMMs in real server environments.
  • Publish research findings regarding telemetry analysis through whitepapers and industry conferences.

What we're looking for

  • Bachelor’s degree with 10+ years of experience, Master’s with 8+ years, or PhD with 5+ years in relevant fields is required.
  • Experience in hardware fault management, reliability, data center fleet management, or related technical fields is preferred.
  • Knowledge of platform memory subsystems and RAS features including ECC, page offlining, hPPR, and hardware sparing.
  • Experience in ECC design, verification, and reverse engineering.
  • Understanding of address mapping between CPU and memory and experience with memory controller register modification.
  • Experience with Linux kernel commits is required.
  • Deep understanding of DRAM and HBM failure modes.

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