Staff Engineer, Memory Systems Architecture

Samsung Semiconductor

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $163,000–$253,000 / yr
Posted: today

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Competitive pay

How this pay compares to similar roles

Similar $193k

This role $208k

$135k most similar roles pay here $266k

This role pays more than 58% of similar roles. Most pay $168,500–$216,562 — the shaded band above. At the midpoint, this role pays about $208k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

Samsung Semiconductor currently has 54 open roles on FindRole.

Listed pay typically runs $163,000–$253,000 across 54 roles with salary data.

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At a glance

TL;DR · Staff Engineer, Memory Systems Architecture

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As a Staff Engineer in Memory Systems Architecture at Samsung Semiconductor, you will join an incubation team focused on enhancing customer quality experience through advanced telemetry analysis for memory products. Your role involves identifying and mitigating DRAM failure modes by developing RAS algorithms such as page offlining and hPPR to minimize system downtime in AI/ML hardware deployments. You will work closely with customers to implement fault management architectures, contribute to industry standards like OCP, and conduct research that may lead to publications. Essential skills include expertise in platform memory subsystems, ECC design, Linux kernel commits, and understanding of DRAM failure modes. This role demands a deep knowledge of SOC controllers, memory operations, and hardware fault management, making it ideal for those passionate about shaping the future of data center reliability and efficiency.

Skills

Linux ECC DRAM HBM Memory Controllers Platform RAS CPU Memory Mapping Fault Management Data Center Fleet Management OCP Standards Virtual Root-Cause Analysis In-Field Telemetry AI/ML Hardware Deployments Whitepapers Conferences

What you'll do

Analyze field DRAM failure data to recommend solutions for mitigating failure rates.
Develop and propose RAS algorithms for memory fault management, including page offlining and hPPR.
Interface with customers to promote the value of in-field fault management architecture.
Standardize DRAM/HBM failure logging within industry standards like OCP.
Conduct proof-of-concept testing with real server and application environments using known failure DIMMs.

What we're looking for

Bachelor’s degree with 10+ years or Master’s with 8+ years in hardware fault management and reliability.
Deep knowledge of platform memory subsystems, including ECC, page offlining, hPPR, and hardware sparing.
Experience with ECC design, verification, and reverse engineering.
Understanding of address mapping between CPU and memory.
Linux kernel commit experience and memory controller register modification skills.
Expertise in analyzing DRAM and HBM failure modes.

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