CPU Microarchitect/RTL Engineer, Execution, Load/Store

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
—
Salary
$150,400–$277,600 / yr
Posted
15 days ago
Freshness
Confirmed live yesterday

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $217k
This role $214k
$135k most similar roles pay here $293k

This role pays more than 52% of similar roles. Most pay $184,900–$250,000 — the shaded band above. At the midpoint, this role pays about $214k versus about $217k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 2925 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2305 roles with salary data.

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At a glance

TL;DR · CPU Microarchitect/RTL Engineer, Execution, Load/Store

The CPU Microarchitect/RTL Engineer - Execution, Load/Store joins the Silicon Engineering Group to drive architecture and RTL development for performant cores. This role involves micro-architecture development and specification from high-level exploration through detailed research, alongside RTL ownership focused on power, performance, area, and timing goals. The engineer will participate in verification support via test bench development and formal methods, conduct performance exploration and correlation, and collaborate with multi-functional teams to ensure physical design reliability. Candidates must possess experience in microprocessor architecture, logic design principles, Verilog or VHDL, and waveform debugging. Preferred skills include expertise in out-of-order execution, instruction scheduling, cache subsystems, and low power techniques. Proficiency in C, C++, Perl, or Python is also valued as the engineer addresses complex challenges in integer, floating-point, and load/store execution for high-performance microprocessors.

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