CPU Microarchitect/RTL Engineer, Fetch, Out of Order

Apple Inc

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Work type
On-site
Location
Beaverton, OR
Posted
40 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

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Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

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TL;DR · CPU Microarchitect/RTL Engineer, Fetch, Out of Order

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The CPU Microarchitect/RTL Engineer - Fetch, Out of Order joins the Silicon Engineering Group to drive architecture and RTL development for performant cores. This role involves owning micro-architecture development and specification, ranging from high-level exploration to detailed research. Key responsibilities include RTL ownership to meet power, performance, area, and timing goals, as well as supporting verification through test bench development, formal methods, and simulation. The engineer will perform performance exploration and correlation while collaborating with multi-functional teams on physical design delivery. Required skills include microprocessor architecture, logic design principles, Verilog or VHDL, and experience with simulators and waveform debugging. Preferred expertise includes instruction fetch, branch prediction, register renaming, out-of-order execution, low power techniques, C, C++, and interpretive languages like Perl or Python.

Skills

RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Formal Methods Simulation Emulation Logic Design Instruction Fetch Branch Prediction Out-of-Order Execution Register Renaming Waveform Debugging

What you'll do

  • Develop and specify micro-architecture from high-level exploration to detailed specifications.
  • Own the development, assessment, and refinement of RTL design to meet power, performance, area, and timing goals.
  • Support the verification team with test bench development, formal methods, and simulation or emulation.
  • Explore high-performance strategies and correlate RTL design against targeted performance metrics.
  • Implement and verify physical design aspects including timing, area, reliability, testability, and power.
  • Design and optimize CPU front-end and out-of-order subsystems for performant cores.

What we're looking for

  • Minimum BS degree and 10+ years of relevant industry experience.
  • Experience with microprocessor architecture.
  • Experience with logic design principles with timing and power implications.
  • Experience in Verilog or VHDL.
  • Experience with simulators and waveform debugging process.
  • Expertise in instruction fetch and decode, branch prediction, instruction scheduling, register renaming, or out-of-order execution (preferred).
  • Understanding of low power microarchitecture techniques (preferred).
  • Understanding of high-performance techniques and trade-offs in a CPU microarchitecture (preferred).

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