CPU Microarchitect/RTL Engineer, Execution, Load/Store

The CPU Microarchitect/RTL Engineer - Execution, Load/Store joins the Silicon Engineering Group to drive architecture and RTL development for performant cores involving integer, floating-point, and load/store execution. This role involves micro-architecture development from high-level exploration through detailed specification, alongside RTL ownership focused on power, performance, area, and timing goals. The engineer will participate in verification support via test bench development, formal methods, and simulation or emulation, while performing performance exploration and correlation to ensure designs meet targets. Key responsibilities include collaborating with multi-functional teams for physical design implementation regarding reliability and testability. Required skills include microprocessor architecture knowledge, logic design principles, Verilog or VHDL, and experience with simulators and waveform debugging. Preferred expertise includes out-of-order execution, instruction scheduling, cache subsystems, low power techniques, C, C++, Perl, or Python.