Apple Inc

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About Apple Inc

Published by FindRole · most recent listing · Methodology

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3546 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2746 roles with salary data.

Most-posted roles

How Apple Inc posts

Employer behavior measured from this employer’s own listings, including ones that have since closed.

77.4%
of open roles publish a salary range

Layoffs · WARN filings

Trending down

1,074 workers affected across 15 filings since 2023.

Source: U.S. Worker Adjustment and Retraining Notification (WARN) Act filings, via WARN Feed (CC BY 4.0).

Open roles

3,546 total

Wireless Design Verification Engineer

Waltham, MA 44 days ago $165,800–$292,400
Actively hiring Confirmed live today Trusted Competitive pay
SystemVerilog UVM Verilog ASIC Verification RTL Verification Python Perl FPGA Palladium Machine Learning AI Bluetooth UWB WLAN Zigbee AMBA Constrained Random Testing Functional Coverage
10+ yrs exp
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Wireless Design Verification Engineer

San Diego, CA 44 days ago $175,000–$308,500
Actively hiring Confirmed live today Trusted Above market
SystemVerilog UVM Verilog ASIC Verification Python Perl FPGA Palladium Machine Learning AI Bluetooth UWB WLAN Zigbee AMBA Constrained Random Testing Functional Coverage
10+ yrs exp
Save

Wireless Design Verification Engineer

San Francisco, CA 44 days ago $184,700–$324,800
Actively hiring Confirmed live today Trusted Above market
SystemVerilog UVM Verilog ASIC Verification Python Perl FPGA Palladium Machine Learning AI Bluetooth UWB WLAN Zigbee AMBA Constrained Random Testing Functional Coverage
10+ yrs exp
Save

PHY Design Verification Engineer

Waltham, MA 44 days ago $165,800–$292,400
Actively hiring Confirmed live yesterday Trusted Above market
SystemVerilog UVM Verilog SystemVerilog Assertion Python Shell Perl Matlab FPGA Palladium ASIC Verification Constrained Random Testing Functional Coverage Machine Learning AI Bluetooth UWB WLAN Zigbee
10+ yrs exp
Save

PHY Design Verification Engineer

San Diego, CA 44 days ago $175,000–$308,500
Actively hiring Confirmed live yesterday Trusted Above market
SystemVerilog UVM Verilog ASIC Verification Python Perl FPGA Palladium Matlab Machine Learning AI Functional Coverage Bluetooth UWB WLAN Zigbee
10+ yrs exp
Save

PHY Design Verification Engineer

San Francisco, CA 44 days ago $184,700–$324,800
Actively hiring Confirmed live today Trusted Above market
SystemVerilog UVM Verilog SystemVerilog Assertion Python Shell Perl Matlab FPGA Palladium ASIC Verification Constrained Random Testing Functional Coverage Machine Learning AI Bluetooth UWB WLAN Zigbee
10+ yrs exp
Save

SerDes Micro Architect

San Diego, CA 44 days ago $175,000–$308,500
Actively hiring Confirmed live today Trusted Above market
SERDES DSP Python MATLAB C C++ Firmware Embedded Software Signal Integrity Machine Learning Simulation Tools Timing Recovery Equalizers
10+ yrs exp
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SerDes Micro Architect

Cupertino, CA 44 days ago $184,700–$324,800
Actively hiring Confirmed live 2 days ago Trusted Above market
SERDES DSP Python MATLAB C C++ Firmware Embedded Software Machine Learning Signal Integrity System Design Simulation Tools Timing Recovery Equalizers
10+ yrs exp
Save

SerDes Micro Architect

Beaverton, OR 44 days ago
Actively hiring Confirmed live yesterday Trusted
SERDES DSP Python MATLAB C C++ Signal Integrity Machine Learning Firmware Embedded Software System Design Simulation Tools Timing Recovery Equalizers
10+ yrs exp
Save

CPU Technology Feasibility Implementation Engineer

Austin, TX 44 days ago
Actively hiring Confirmed live today Low trust
RTL-to-GDS Synthesis place-and-route PnR PPA Optimization CPU Microarchitecture Clock Flow Physical Design Memory Design Process Technology Evaluation
10+ yrs exp
Save

WSoC PHY/MAC Validation and Integration Engineer

San Diego, CA 44 days ago $175,000–$308,500
Actively hiring Confirmed live today High trust Above market
DSP PHY MAC Python FPGA Bluetooth Zigbee UWB WLAN RF RTL Signal Modulation Error Correction Spectrum Analyzer Network Analyzer Oscilloscope Constrained Random Testing Hardware Debugging
10+ yrs exp
Save

WSoC PHY/MAC Validation and Integration Engineer

San Francisco, CA 44 days ago $184,700–$324,800
Actively hiring Confirmed live today High trust Above market
DSP PHY Layer RF MAC Python FPGA Bluetooth Zigbee UWB WLAN RTL Signal Modulation Error Correction Spectrum Analyzer Network Analyzer Oscilloscope Constrained Random Testing Hardware Debugging
10+ yrs exp
Save

CPU ML Microarchitect/RTL Engineer

Santa Clara, CA 44 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Trusted Above market
RTL Verilog VHDL Microarchitecture C C++ Python Perl Logic Design Formal Methods Simulation Emulation Waveform Debugging Out-of-Order Execution Instruction Scheduling
10+ yrs exp
Save

CPU ML Microarchitect/RTL Engineer

Santa Clara, CA 44 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Trusted Competitive pay
RTL Verilog VHDL Microarchitecture C C++ Python Perl Logic Design Formal Methods Simulation Emulation Waveform Debugging Out-of-Order Execution Instruction Scheduling
3+ yrs exp
Save

CPU Microarchitect/RTL Engineer, Execution, Load/Store

Waltham, MA 44 days ago $165,800–$292,400
Actively hiring Confirmed live today Trusted Competitive pay
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Logic Design Formal Methods Simulation Emulation Out-of-Order Execution Instruction Scheduling Load/Store Execution
10+ yrs exp
Save

CPU Microarchitect/RTL Engineer, Execution, Load/Store

Santa Clara, CA 44 days ago $184,700–$324,800
Actively hiring Confirmed live today Trusted Above market
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Logic Design Formal Methods Simulation Emulation Out-of-Order Execution Instruction Scheduling Waveform Debugging
10+ yrs exp
Save

CPU Microarchitect/RTL Engineer, Execution, Load/Store

Beaverton, OR 44 days ago
Actively hiring Confirmed live today Low trust
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Logic Design Formal Methods Simulation Emulation Out-of-Order Execution Instruction Scheduling Cache Memory Subsystems Waveform Debugging
10+ yrs exp
Save

CPU Microarchitect/RTL Engineer, Execution, Load/Store

Santa Clara, CA 44 days ago $150,400–$277,600
Actively hiring Confirmed live today Trusted Competitive pay
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Logic Design Formal Methods Simulation Emulation Waveform Debugging Out-of-Order Execution Instruction Scheduling Load/Store Execution
3+ yrs exp
Save

CPU Microarchitect/RTL Engineer, Fetch, Out of Order

Santa Clara, CA 44 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Trusted Competitive pay
RTL Verilog VHDL Microarchitecture Out-of-Order Execution C C++ Python Perl Formal Methods Simulation Emulation Logic Design Waveform Debugging
3+ yrs exp
Save

CPU Design Verification Engineer

Austin, TX 44 days ago
Actively hiring Confirmed live yesterday Low trust
SystemVerilog C C++ Assembly CPU Architecture Digital Logic Design Microarchitecture Post-silicon Bringup
10+ yrs exp
Save