PHY Design Verification Engineer

Apple Inc

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: San Francisco, CA
Salary: $184,700–$324,800 / yr
Posted: 17 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $198k

This role $255k

$129k most similar roles pay here $346k

This role pays more than 98% of similar roles. Most pay $168,500–$227,900 — the shaded band above. At the midpoint, this role pays about $255k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2740 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · PHY Design Verification Engineer

Role Posting Log in to save

PHY Design Verification Engineer The PHY Design Verification Engineer joins the wireless silicon development team to perform pre-silicon RTL verification of wireless PHY and its interfaces with the broader wireless communication SoC. This role involves collaborating with DV methodologists, designers, and systems engineers to develop reusable test benches and verification environments using metric-driven methodologies. Key responsibilities include creating verification plans from specifications, executing directed and constrained random tests, managing bug tracking, and analyzing coverage models. The candidate will utilize Verilog, SystemVerilog, UVM, and SystemVerilog Assertions, alongside Matlab/C reference models for bit-accurate verification. Technical skills required include Python, Shell, and Perl scripting, as well as experience with Palladium, FPGA validation, and AI technologies for data mining. The role focuses on the technical challenge of ensuring high design quality for wireless communication subsystems including Bluetooth, UWB, WLAN, or Zigbee protocols.

Skills

SystemVerilog UVM Verilog SystemVerilog Assertion Python Shell Perl Matlab FPGA Palladium Machine Learning AI RTL Verification Constrained Random Testing Functional Coverage Bluetooth UWB WLAN Zigbee

What you'll do

Create verification plans from specifications and refine them to achieve coverage targets.
Build reusable block and subsystem level test benches using best-in-class DV methodology.
Develop and execute directed and constrained random tests for the wireless PHY.
Debug failures, manage bug tracking, and work with designers to resolve issues.
Create and analyze coverage models while adding test cases to increase coverage.
Utilize machine learning and AI technologies to identify design and test bench issues.
Support PHY subsystem validation using Palladium and FPGA platforms.
Improve overall DV methodology and flow through collaboration with team members.

What we're looking for

Bachelor of Science degree.
Minimum of 10 years of relevant industry experience.
Experience with wireless or wired communication block/subsystem verification (preferred).
Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion (preferred).
Knowledge of ASIC verification flows including test bench development, constrained random testing, and coverage (preferred).
Proficiency in shell, Python, and Perl scripting (preferred).
Experience with Matlab/C reference models, bit-accurate verification, and Palladium or FPGA validation (preferred).
Knowledge of wireless protocols like Bluetooth, UWB, WLAN, or Zigbee; and experience using AI for data mining (preferred).

Similar roles

PHY Design Verification Engineer

Apple Inc

Waltham, MA 17 days ago $165,800–$292,400

SystemVerilog UVM Verilog SystemVerilog Assertion Python Shell Perl Matlab FPGA Palladium Machine Learning AI RTL Verification Constrained Random Testing Bluetooth UWB WLAN Zigbee

10+ yrs exp

Save

PHY Design Verification Engineer

Apple Inc

San Diego, CA 17 days ago $175,000–$308,500

SystemVerilog UVM Verilog SystemVerilog Assertion Python Shell Perl Matlab FPGA Palladium Machine Learning AI RTL Verification Constrained Random Testing Bluetooth WLAN Zigbee UWB

10+ yrs exp

Save

PHY Design Verification Engineer

Apple Inc

San Francisco, CA 79 days ago $129,300–$225,300

SystemVerilog UVM Verilog ASIC Verification Python Perl FPGA Palladium Matlab Machine Learning AI Bluetooth UWB WLAN Zigbee Constrained Random Testing

Save

PHY Design Verification Engineer

Apple Inc

San Diego, CA 79 days ago $122,700–$214,300

SystemVerilog UVM Verilog SystemVerilog Assertion Python Perl Matlab FPGA Palladium Machine Learning AI RTL Verification Constrained Random Testing Bluetooth WLAN Zigbee UWB

Save

Wireless Design Verification Engineer

Apple Inc

San Francisco, CA 17 days ago $184,700–$324,800

SystemVerilog UVM Verilog ASIC Verification Python Perl FPGA Palladium Machine Learning AI Bluetooth WLAN Zigbee UWB AMBA RTL Verification Constrained Random Testing

10+ yrs exp

Save

Wireless Design Verification Engineer

Apple Inc

San Diego, CA 17 days ago $175,000–$308,500

SystemVerilog UVM Verilog ASIC Verification Python Perl FPGA Palladium Machine Learning AI Bluetooth WLAN Zigbee UWB AMBA RTL Constrained Random Testing

10+ yrs exp

Save