Wireless Design Verification Engineer

Apple Inc

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: Waltham, MA
Salary: $165,800–$292,400 / yr
Posted: 17 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $205k

This role $229k

$133k most similar roles pay here $309k

This role pays more than 67% of similar roles. Most pay $168,500–$241,750 — the shaded band above. At the midpoint, this role pays about $229k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2740 roles with salary data.

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At a glance

TL;DR · Wireless Design Verification Engineer

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Wireless Design Verification Engineer will join the wireless silicon development team to perform pre-silicon RTL verification of wireless MAC and its interfaces with the rest of the wireless SoC. The role involves collaborating with methodologists, designers, and communication systems engineers to develop reusable test benches and verification environments using metric-driven methodology. Key responsibilities include creating verification plans from specifications, building UVM libraries, executing directed and constrained random tests, managing bug tracking, and analyzing coverage models. The candidate will utilize Verilog, SystemVerilog, UVM, SystemVerilog Assertion, and scripting languages like Python, Shell, and Perl. Additionally, the role involves using machine learning for data mining and performing validation on Palladium or FPGA hardware. This position addresses technical challenges in wireless communication subsystems involving protocols such as Bluetooth, UWB, WLAN, or Zigbee to ensure high-quality silicon design.

Skills

SystemVerilog UVM Verilog ASIC Verification RTL Python Perl FPGA Palladium Machine Learning AI Bluetooth WLAN Zigbee UWB AMBA Constrained Random Testing

What you'll do

Create verification plans from specifications and refine them to achieve coverage targets for the MAC subsystem.
Build block and subsystem level test benches using UVM libraries and best-in-class DV methodologies.
Develop and execute directed and constrained random tests to identify and debug design failures.
Manage bug tracking and work with designers to drive the closure of identified issues.
Create and analyze coverage models while adding specific test cases to increase overall coverage.
Utilize machine learning and AI technologies to identify design issues and ensure verification quality.
Support MAC subsystem validation using Palladium and FPGA platforms.
Improve internal DV methodologies and workflows through collaboration with team members.

What we're looking for

Bachelor of Science degree and at least 10 years of relevant industry experience.
Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion (preferred).
Experience with ASIC verification flows including test bench development, constrained random testing, and coverage (preferred).
Verification experience of wireless/wired communication block/subsystem (preferred).
7+ years of verification experience specifically for wireless/wired communication blocks or subsystems (preferred).
Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee (preferred).
Proficiency in shell, Python, and Perl scripting (preferred).
Experience with Palladium/FPGA validation and AI technologies for data mining or analysis (preferred).

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